Thanks @zhanghaohit

I like to have your opinion on using soft cores for pcie based fpgas. Rather 
than going through the high latency communications between the host and fpga or 
as you did running all the middle layers on the fpga itself, we can offload 
runtime stuff on a soft core (nios, microblaze, or better a riscv core). what's 
the downsides here?





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