Seems like we are converging.

Another aspect that @thierry mentioned, and I would like to extend a bit that 
we need to make sure that each design entry can follow a VTA spec via regular 
CI testing. For now the unit test and integration test script ensures the 
correctness of the existing three design entries, e.g. HLS based design entry 
is checked via FPGA based testing, C based design entry is checked via FSim, 
Chisel-based design entry is checked via TSIM. I think the proposed 
OpenCL-based design entry should fit into existing CI testing framework.





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