[quote="thierry, post:14, topic:6676, full:true"]
Finally some lower level comments for @zhanghaohit and @remotego:

* I agree with @liangfu that leveraging Chisel would be ideal in the spirit of 
minimizing the number of design sources. There is an initial scaffold of the 
Chisel design to work on F1 FPGAs, which @vegaluis can share with you.
* I would leave the question of multi core parallelism brought up by @liangu 
for a follow up RFC. For now if we can instantiate a larger GEMM core (e.g. 
32x32 or 64x64) on an F1 FPGA it would be a good step forward.
* I do like the idea of supporting residual layers and also max pooling in VTA. 
The hardware machinery for max pooling is there but not the compiler support. 
It makes sense to support 8bit load into ACC if we want to support residual 
layers. Alternatively, we could support a 32bit store in VTA of ACC data, and 
keep computation in 32bits for residual layers.
* Several new features have been introduced that will make graph partitioning a 
little easier for VTA: consider using the newly introduced Pattern Matching 
feature in Relay to identify subgraphs that can be offloaded to VTA: 
https://docs.tvm.ai/langref/relay_pattern.html
* In addition in order to automate the copy of data between the devices, 
consider leveraging the heterogeneous runtime. This PR has some examples on how 
the runtime can be used: https://github.com/apache/incubator-tvm/pull/1695
* Finally, you may want to consider consider unifying the device api for VTA 
([https://github.com/apache/incubator-tvm/blob/master/vta/runtime/device_api.cc 
](https://github.com/apache/incubator-tvm/blob/master/vta/runtime/device_api.cc))
 to support both SoC type and PCI-E type FPGAs.
[/quote]

Thanks @thierry for the suggestions and detailed information.





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