From: Andy Moreton <andy.more...@amd.com>
Add support for 8 port mode and adjust the bus bandwidth
computation and external port mapping table.
Signed-off-by: Andy Moreton <andy.more...@amd.com>
Reviewed-by: Ivan Malov <ivan.ma...@arknetworks.am>
---
drivers/common/sfc_efx/base/ef10_nic.c | 20 +++++++++++++++++++
drivers/common/sfc_efx/base/ef10_tlv_layout.h | 9 ++++++---
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/drivers/common/sfc_efx/base/ef10_nic.c
b/drivers/common/sfc_efx/base/ef10_nic.c
index 9bff68f054..afad167dcb 100644
--- a/drivers/common/sfc_efx/base/ef10_nic.c
+++ b/drivers/common/sfc_efx/base/ef10_nic.c
@@ -176,6 +176,9 @@ ef10_nic_get_port_mode_bandwidth(
case TLV_PORT_MODE_2x1_2x1: /* mode 5 */
bandwidth = (2 * single_lane) + (2 * single_lane);
break;
+ case TLV_PORT_MODE_4x1_4x1: /* mode 26 */
+ bandwidth = (4 * single_lane) + (4 * single_lane);
+ break;
case TLV_PORT_MODE_1x2_1x2: /* mode 12 */
bandwidth = dual_lane + dual_lane;
break;
@@ -1952,6 +1955,23 @@ static struct ef10_external_port_map_s {
(1U << TLV_PORT_MODE_4x1_NA), /* mode 4 */
{ 0, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
},
+ /*
+ * Modes that on Medford4 allocate up to 4 adjacent port numbers
+ * to cage 1 and 4 port numbers to cage 2.
+ * port 0 -> cage 1
+ * port 1 -> cage 1
+ * port 2 -> cage 1
+ * port 3 -> cage 1
+ * port 4 -> cage 2
+ * port 5 -> cage 2
+ * port 6 -> cage 2
+ * port 7 -> cage 2
+ */
+ {
+ EFX_FAMILY_MEDFORD4,
+ (1U << TLV_PORT_MODE_4x1_4x1), /* mode 26 */
+ { 0, 4, EFX_EXT_PORT_NA, EFX_EXT_PORT_NA }
+ },
};
static __checkReturn efx_rc_t
diff --git a/drivers/common/sfc_efx/base/ef10_tlv_layout.h
b/drivers/common/sfc_efx/base/ef10_tlv_layout.h
index 9ac50f1df6..712a1c7d26 100644
--- a/drivers/common/sfc_efx/base/ef10_tlv_layout.h
+++ b/drivers/common/sfc_efx/base/ef10_tlv_layout.h
@@ -7,7 +7,7 @@
/*
* This is NOT the original source file. Do NOT edit it.
* To update the tlv layout, please edit the copy in
- * the sfregistry repo and then, in that repo,
+ * the smartnic_registry repo and then, in that repo,
* "make tlv_headers" or "make export" to
* regenerate and export all types of headers.
*/
@@ -635,7 +635,10 @@ struct tlv_global_port_mode {
#define TLV_PORT_MODE_1x1_NA_LL (23) /* Single 10G/25G on
mdi0, low-latency PCS */
#define TLV_PORT_MODE_1x1_1x1_LL (24) /* Single 10G/25G on
mdi0, single 10G/25G on mdi1, low-latency PCS */
#define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
-#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
+
+/* X4 */
+
+#define TLV_PORT_MODE_4x1_4x1 (25) /* Quad 10G/25G on mdi0,
quad 10G/25G on mdi1 */
/* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5)
@@ -643,7 +646,7 @@ struct tlv_global_port_mode {
#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8)
#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9)
-#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
+#define TLV_PORT_MODE_MAX TLV_PORT_MODE_4x1_4x1
};
/* Type of the v-switch created implicitly by the firmware */
--
2.39.5
