From: Danylo Vodopianov <dvo-...@napatech.com>
Add initialization for I/O expanders and configure TS settings.
Signed-off-by: Danylo Vodopianov <dvo-...@napatech.com>
---
.../ntnic/nthw/core/include/nthw_pcal6416a.h | 3 +
.../nt400dxx/reset/nthw_fpga_rst_nt400dxx.c | 69 +++++++++++++++++++
drivers/net/ntnic/nthw/core/nthw_pcal6416a.c | 23 +++++++
drivers/net/ntnic/nthw/nthw_drv.h | 1 +
4 files changed, 96 insertions(+)
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_pcal6416a.h
b/drivers/net/ntnic/nthw/core/include/nthw_pcal6416a.h
index a718b59a29..e3dadcc8e3 100644
--- a/drivers/net/ntnic/nthw/core/include/nthw_pcal6416a.h
+++ b/drivers/net/ntnic/nthw/core/include/nthw_pcal6416a.h
@@ -24,6 +24,9 @@ struct nthw_pcal6416a {
typedef struct nthw_pcal6416a nthw_pcal6416a_t;
+nthw_pcal6416a_t *nthw_pcal6416a_new(void);
+int nthw_pcal6416a_init(nthw_pcal6416a_t *p, nthw_i2cm_t *p_nt_i2cm, uint8_t
dev_address,
+ nthw_pca9849_t *pca9849, uint8_t mux_channel);
void nthw_pcal6416a_write(nthw_pcal6416a_t *p, uint8_t pin, uint8_t value);
void nthw_pcal6416a_read(nthw_pcal6416a_t *p, uint8_t pin, uint8_t *value);
diff --git
a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
index 6c5c1cd51e..c8fd37d0ff 100644
--- a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
+++ b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
@@ -86,6 +86,58 @@ static int nthw_fpga_rst_nt400dxx_init(struct fpga_info_s
*p_fpga_info)
if (res != 0)
return res;
+ /* Create PCAL6416A I/O expander for controlling Nim */
+ p_fpga_info->mp_nthw_agx.p_io_nim = nthw_pcal6416a_new();
+ res = nthw_pcal6416a_init(p_fpga_info->mp_nthw_agx.p_io_nim,
+ p_fpga_info->mp_nthw_agx.p_i2cm,
+ 0x20,
+ p_fpga_info->mp_nthw_agx.p_pca9849,
+ 3);
+
+ if (res != 0)
+ return res;
+
+ /* Create PCAL6416A I/O expander for controlling TS */
+ p_fpga_info->mp_nthw_agx.p_io_ts = nthw_pcal6416a_new();
+ res = nthw_pcal6416a_init(p_fpga_info->mp_nthw_agx.p_io_ts,
+ p_fpga_info->mp_nthw_agx.p_i2cm,
+ 0x20,
+ p_fpga_info->mp_nthw_agx.p_pca9849,
+ 2);
+
+ if (res != 0)
+ return res;
+
+ /*
+ * disable pps out
+ * TS_EXT1_OUT_EN : Low
+ */
+ nthw_pcal6416a_write(p_fpga_info->mp_nthw_agx.p_io_ts, 0, 0);
+
+ /*
+ * Enable DC termination
+ * TS_EXT1_TERM_DC_E : High
+ */
+ nthw_pcal6416a_write(p_fpga_info->mp_nthw_agx.p_io_ts, 3, 1);
+
+ /*
+ * enable 50 ohm termination
+ * TS_EXT1_TERM50_DIS : low
+ */
+ nthw_pcal6416a_write(p_fpga_info->mp_nthw_agx.p_io_ts, 2, 0);
+
+ /*
+ * Normal Threshold
+ * TS_EXT1_LOW_THRESHOLD: Low
+ */
+ nthw_pcal6416a_write(p_fpga_info->mp_nthw_agx.p_io_ts, 1, 0);
+
+ /*
+ * Select FPGA I/O - we want to use TSM Bresenham for time adjustments
against PPS time
+ * reference TS_EXT_ZL30733_EnB: High
+ */
+ nthw_pcal6416a_write(p_fpga_info->mp_nthw_agx.p_io_ts, 8, 1);
+
/* Create LED driver */
p_fpga_info->mp_nthw_agx.p_pca9532_led = nthw_pca9532_new();
res = nthw_pca9532_init(p_fpga_info->mp_nthw_agx.p_pca9532_led,
@@ -100,6 +152,23 @@ static int nthw_fpga_rst_nt400dxx_init(struct fpga_info_s
*p_fpga_info)
for (uint8_t i = 0; i < 16; i++)
nthw_pca9532_set_led_on(p_fpga_info->mp_nthw_agx.p_pca9532_led,
i, false);
+ /* Enable power supply to NIMs */
+ nthw_pcal6416a_write(p_fpga_info->mp_nthw_agx.p_io_nim, 8, 1);
+ nt_os_wait_usec(100000);/* 100ms */
+
+ /* Check that power supply turned on. Warn if it didn't. */
+ uint8_t port_power_ok;
+ nthw_pcal6416a_read(p_fpga_info->mp_nthw_agx.p_io_nim, 9,
&port_power_ok);
+
+ if (port_power_ok != 1) {
+ NT_LOG(ERR,
+ NTHW,
+ "Warning: Power supply for QSFP modules did not turn on
- Fuse might be blown.");
+ return -1;
+ }
+
+ NT_LOG(INF, NTHW, "Status of power supply for QSFP modules %u",
port_power_ok);
+
/* Create PCM */
p_fpga_info->mp_nthw_agx.p_pcm = nthw_pcm_nt400dxx_new();
res = nthw_pcm_nt400dxx_init(p_fpga_info->mp_nthw_agx.p_pcm, p_fpga, 0);
diff --git a/drivers/net/ntnic/nthw/core/nthw_pcal6416a.c
b/drivers/net/ntnic/nthw/core/nthw_pcal6416a.c
index dd803ac66d..2fca469497 100644
--- a/drivers/net/ntnic/nthw/core/nthw_pcal6416a.c
+++ b/drivers/net/ntnic/nthw/core/nthw_pcal6416a.c
@@ -20,6 +20,29 @@ static const uint8_t config_port[2] = { 0x06, 0x07 };
* PCAL6416A I/O expander class
*/
+nthw_pcal6416a_t *nthw_pcal6416a_new(void)
+{
+ nthw_pcal6416a_t *p = malloc(sizeof(nthw_pcal6416a_t));
+
+ if (p) {
+ memset(p, 0, sizeof(nthw_pcal6416a_t));
+ p->m_config_data[0] = 0xFF;
+ p->m_config_data[1] = 0xFF;
+ }
+
+ return p;
+}
+
+int nthw_pcal6416a_init(nthw_pcal6416a_t *p, nthw_i2cm_t *p_nt_i2cm, uint8_t
dev_address,
+ nthw_pca9849_t *pca9849, uint8_t mux_channel)
+{
+ p->mp_nt_i2cm = p_nt_i2cm;
+ p->m_dev_address = dev_address;
+ p->mp_ca9849 = pca9849;
+ p->m_mux_channel = mux_channel;
+ return 0;
+}
+
void nthw_pcal6416a_write(nthw_pcal6416a_t *p, uint8_t pin, uint8_t value)
{
uint8_t port;
diff --git a/drivers/net/ntnic/nthw/nthw_drv.h
b/drivers/net/ntnic/nthw/nthw_drv.h
index ecd3bb9cc4..574dd663ea 100644
--- a/drivers/net/ntnic/nthw/nthw_drv.h
+++ b/drivers/net/ntnic/nthw/nthw_drv.h
@@ -24,6 +24,7 @@
typedef struct nthw_agx_s {
nthw_i2cm_t *p_i2cm;
nthw_pca9849_t *p_pca9849;
+ nthw_pcal6416a_t *p_io_ts; /* PCAL6416A I/O expander for
controlling TS */
nthw_pcal6416a_t *p_io_nim; /* PCAL6416A I/O expander for
controlling TS */
nthw_pca9532_t *p_pca9532_led;
nthw_si5332_t *p_si5332;
--
2.45.0
