From: Danylo Vodopianov <dvo-...@napatech.com>
Add HIF clock test with write/read verification.
Signed-off-by: Danylo Vodopianov <dvo-...@napatech.com>
---
.../net/ntnic/nthw/core/include/nthw_hif.h | 3 +
.../nt400dxx/reset/nthw_fpga_rst_nt400dxx.c | 20 +++++
drivers/net/ntnic/nthw/core/nthw_hif.c | 82 +++++++++++++++++++
3 files changed, 105 insertions(+)
diff --git a/drivers/net/ntnic/nthw/core/include/nthw_hif.h
b/drivers/net/ntnic/nthw/core/include/nthw_hif.h
index c8f4669f83..deb9ed04e8 100644
--- a/drivers/net/ntnic/nthw/core/include/nthw_hif.h
+++ b/drivers/net/ntnic/nthw/core/include/nthw_hif.h
@@ -148,4 +148,7 @@ int nthw_hif_get_stat_rate(nthw_hif_t *p, uint64_t
*p_pci_rx_rate, uint64_t *p_p
int nthw_hif_end_point_counters_sample(nthw_hif_t *p, struct
nthw_hif_end_point_counters *epc);
+int nthw_hif_read_test_reg(nthw_hif_t *p, uint8_t test_reg, uint32_t *p_value);
+int nthw_hif_write_test_reg(nthw_hif_t *p, uint8_t test_reg, uint32_t value);
+
#endif /* __NTHW_HIF_H__ */
diff --git
a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
index 1d93474cff..60e7714283 100644
--- a/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
+++ b/drivers/net/ntnic/nthw/core/nt400dxx/reset/nthw_fpga_rst_nt400dxx.c
@@ -24,6 +24,26 @@ static int nthw_fpga_rst_nt400dxx_init(struct fpga_info_s
*p_fpga_info)
if (res == 0)
NT_LOG(DBG, NTHW, "%s: Hif module found",
p_fpga_info->mp_adapter_id_str);
+ /* (A) Test HIF clock is running by performing simple write/read test
of HIF registers */
+ const uint32_t test_pattern[2] = { 0x11223344, 0x55667788 };
+
+ for (uint8_t i = 0; i < 2; ++i) {
+ uint32_t test_data = 0;
+ nthw_hif_write_test_reg(p_nthw_hif, i, test_pattern[i]);
+ nthw_hif_read_test_reg(p_nthw_hif, i, &test_data);
+
+ if (test_data != test_pattern[i]) {
+ NT_LOG(ERR,
+ NTHW,
+ "%s: %s: Test sys 250 clock failed",
+ p_fpga_info->mp_adapter_id_str,
+ __func__);
+ return -1;
+ }
+ }
+
+ nthw_hif_delete(p_nthw_hif);
+
/* Create PCM */
p_fpga_info->mp_nthw_agx.p_pcm = nthw_pcm_nt400dxx_new();
res = nthw_pcm_nt400dxx_init(p_fpga_info->mp_nthw_agx.p_pcm, p_fpga, 0);
diff --git a/drivers/net/ntnic/nthw/core/nthw_hif.c
b/drivers/net/ntnic/nthw/core/nthw_hif.c
index 9f699e4f94..92a2348bbb 100644
--- a/drivers/net/ntnic/nthw/core/nthw_hif.c
+++ b/drivers/net/ntnic/nthw/core/nthw_hif.c
@@ -298,3 +298,85 @@ int nthw_hif_end_point_counters_sample(nthw_hif_t *p,
struct nthw_hif_end_point_
return 0;
}
+
+int nthw_hif_read_test_reg(nthw_hif_t *p, uint8_t test_reg, uint32_t *p_value)
+{
+ uint32_t data;
+
+ switch (test_reg) {
+ case 0:
+ data = nthw_field_get_updated(p->mp_fld_pci_test0);
+ break;
+
+ case 1:
+ data = nthw_field_get_updated(p->mp_fld_pci_test1);
+ break;
+
+ case 2:
+ if (p->mp_fld_pci_test2)
+ data = nthw_field_get_updated(p->mp_fld_pci_test2);
+
+ else
+ return -1;
+
+ break;
+
+ case 3:
+ if (p->mp_fld_pci_test3)
+ data = nthw_field_get_updated(p->mp_fld_pci_test3);
+
+ else
+ return -1;
+
+ break;
+
+ default:
+ assert(false);
+ return -1;
+ }
+
+ if (p_value)
+ *p_value = data;
+
+ else
+ return -1;
+
+ return 0;
+}
+
+int nthw_hif_write_test_reg(nthw_hif_t *p, uint8_t test_reg, uint32_t value)
+{
+ switch (test_reg) {
+ case 0:
+ nthw_field_set_val_flush32(p->mp_fld_pci_test0, value);
+ break;
+
+ case 1:
+ nthw_field_set_val_flush32(p->mp_fld_pci_test1, value);
+ break;
+
+ case 2:
+ if (p->mp_fld_pci_test2)
+ nthw_field_set_val_flush32(p->mp_fld_pci_test2, value);
+
+ else
+ return -1;
+
+ break;
+
+ case 3:
+ if (p->mp_fld_pci_test3)
+ nthw_field_set_val_flush32(p->mp_fld_pci_test3, value);
+
+ else
+ return -1;
+
+ break;
+
+ default:
+ assert(false);
+ return -1;
+ }
+
+ return 0;
+}
--
2.45.0
