From: Ian Stokes <ian.sto...@intel.com>
Assign the ETH56G PHY address according to the PCI IDs in preparation for
further changes.
Signed-off-by: Sergey Temerkhanov <sergey.temerkha...@intel.com>
Signed-off-by: Ian Stokes <ian.sto...@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 39 +++++++++++++++++++-----------
drivers/net/ice/base/ice_ptp_hw.h | 2 +-
drivers/net/ice/base/ice_sbq_cmd.h | 2 +-
drivers/net/ice/base/ice_type.h | 1 +
4 files changed, 28 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 1b4534d127..5be4abb73d 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -940,7 +940,7 @@ ice_write_phy_eth56g_raw_lp(struct ice_hw *hw, u32
reg_addr, u32 val,
phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);
phy_msg.data = val;
- phy_msg.dest_dev = phy_56g;
+ phy_msg.dest_dev = hw->phy_addr;
err = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
@@ -970,7 +970,7 @@ ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr,
u32 *val,
phy_msg.msg_addr_low = ICE_LO_WORD(reg_addr);
phy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);
- phy_msg.dest_dev = phy_56g;
+ phy_msg.dest_dev = hw->phy_addr;
err = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);
@@ -2291,6 +2291,8 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw,
u32 *ts_err)
return 0;
}
+#define ICE_DEVID_MASK 0xFFF8
+
/**
* ice_ptp_init_phy_model - Initialize hw->phy_model based on device type
* @hw: pointer to the HW struct
@@ -2298,31 +2300,40 @@ ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw
*hw, u32 *ts_err)
* Determine the PHY configuration for the device, and initialize hw->phy_model
* for use by other functions.
*/
-int ice_ptp_init_phy_model(struct ice_hw *hw)
+void ice_ptp_init_phy_model(struct ice_hw *hw)
{
- int err;
u32 phy_rev;
- ice_sb_access_ena_eth56g(hw, true);
+ switch (hw->device_id & ICE_DEVID_MASK) {
+ case ICE_DEV_ID_E825C_BACKPLANE & ICE_DEVID_MASK:
+ hw->phy_addr = eth56g_dev_0;
+ break;
+ default:
+ hw->phy_addr = 0;
+ }
- err = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION, &phy_rev,
- true);
- if (err)
- return err;
+ if (hw->phy_addr) {
+ int err;
- if (phy_rev == PHY_REVISION_ETH56G) {
- hw->phy_model = ICE_PHY_ETH56G;
- return 0;
+ ice_sb_access_ena_eth56g(hw, true);
+ err = ice_read_phy_eth56g_raw_lp(hw, PHY_REG_REVISION,
+ &phy_rev, true);
+ if (err)
+ return;
+
+ if (phy_rev == PHY_REVISION_ETH56G) {
+ hw->phy_model = ICE_PHY_ETH56G;
+ return;
+ }
}
if (ice_is_e810(hw))
hw->phy_model = ICE_PHY_E810;
else
hw->phy_model = ICE_PHY_E822;
+
hw->phy_ports = ICE_NUM_EXTERNAL_PORTS;
hw->max_phy_port = ICE_NUM_EXTERNAL_PORTS;
-
- return 0;
}
/* E822 family functions
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index 0684d1516d..952e7966a3 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -301,7 +301,7 @@ ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool
bypass);
int ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);
int ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);
-int ice_ptp_init_phy_model(struct ice_hw *hw);
+void ice_ptp_init_phy_model(struct ice_hw *hw);
#define PFTSYN_SEM_BYTES 4
diff --git a/drivers/net/ice/base/ice_sbq_cmd.h
b/drivers/net/ice/base/ice_sbq_cmd.h
index 4da16caf70..aad77af9a1 100644
--- a/drivers/net/ice/base/ice_sbq_cmd.h
+++ b/drivers/net/ice/base/ice_sbq_cmd.h
@@ -48,7 +48,7 @@ struct ice_sbq_evt_desc {
};
enum ice_sbq_msg_dev {
- phy_56g = 0x02,
+ eth56g_dev_0 = 0x02,
rmn_0 = 0x02,
rmn_1 = 0x03,
rmn_2 = 0x04,
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 7bada1dd5b..67ea9f9038 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -1269,6 +1269,7 @@ struct ice_hw {
u8 pf_id; /* device profile info */
enum ice_phy_model phy_model;
+ u8 phy_addr; /* PHY address */
u8 phy_ports;
u8 max_phy_port;
u8 logical_pf_id;
--
2.43.0
