From: Ian Stokes <ian.sto...@intel.com>
The upstream driver placed the ice_read_sma_ctrl_e810t and
ice_write_sma_ctrl_e810t functions before the ice_read_pca9575_reg_e810t
function.
Align with upstream and order the functions so that the sma functions come
before the pca9575 functions, slightly reducing the difference between upstream
and out-of-tree.
Signed-off-by: Jacob Keller <jacob.e.kel...@intel.com>
Signed-off-by: Ian Stokes <ian.sto...@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 135 +++++++++++++++---------------
drivers/net/ice/base/ice_ptp_hw.h | 7 +-
2 files changed, 71 insertions(+), 71 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index db28aa308c..bd759a0e83 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -5153,70 +5153,6 @@ bool ice_is_gps_present_e810t(struct ice_hw *hw)
return true;
}
-/**
- * ice_read_pca9575_reg_e810t
- * @hw: pointer to the hw struct
- * @offset: GPIO controller register offset
- * @data: pointer to data to be read from the GPIO controller
- *
- * Read the register from the GPIO controller
- */
-int
-ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data)
-{
- struct ice_aqc_link_topo_addr link_topo;
- int status;
- __le16 addr;
- u16 handle;
-
- memset(&link_topo, 0, sizeof(link_topo));
-
- status = ice_get_pca9575_handle(hw, &handle);
- if (status)
- return status;
-
- link_topo.handle = CPU_TO_LE16(handle);
- link_topo.topo_params.node_type_ctx =
- (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
- ICE_AQC_LINK_TOPO_NODE_CTX_S);
-
- addr = CPU_TO_LE16((u16)offset);
-
- return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);
-}
-
-/**
- * ice_write_pca9575_reg_e810t
- * @hw: pointer to the hw struct
- * @offset: GPIO controller register offset
- * @data: data to be written to the GPIO controller
- *
- * Write the data to the GPIO controller register
- */
-int
-ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data)
-{
- struct ice_aqc_link_topo_addr link_topo;
- __le16 addr;
- int status;
- u16 handle;
-
- memset(&link_topo, 0, sizeof(link_topo));
-
- status = ice_get_pca9575_handle(hw, &handle);
- if (status)
- return status;
-
- link_topo.handle = CPU_TO_LE16(handle);
- link_topo.topo_params.node_type_ctx =
- (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
- ICE_AQC_LINK_TOPO_NODE_CTX_S);
-
- addr = CPU_TO_LE16((u16)offset);
-
- return ice_aq_write_i2c(hw, link_topo, 0, addr, 1, &data, NULL);
-}
-
/**
* ice_read_sma_ctrl_e810t
* @hw: pointer to the hw struct
@@ -5236,10 +5172,10 @@ int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)
*data = 0;
- for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) {
+ for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
bool pin;
- status = ice_aq_get_gpio(hw, handle, i + ICE_E810T_P1_OFFSET,
+ status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
&pin, NULL);
if (status)
break;
@@ -5266,11 +5202,11 @@ int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
if (status)
return status;
- for (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) {
+ for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) {
bool pin;
pin = !(data & (1 << i));
- status = ice_aq_set_gpio(hw, handle, i + ICE_E810T_P1_OFFSET,
+ status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET,
pin, NULL);
if (status)
break;
@@ -5279,6 +5215,69 @@ int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)
return status;
}
+/**
+ * ice_read_pca9575_reg_e810t
+ * @hw: pointer to the hw struct
+ * @offset: GPIO controller register offset
+ * @data: pointer to data to be read from the GPIO controller
+ *
+ * Read the register from the GPIO controller
+ */
+int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data)
+{
+ struct ice_aqc_link_topo_addr link_topo;
+ __le16 addr;
+ u16 handle;
+ int err;
+
+ memset(&link_topo, 0, sizeof(link_topo));
+
+ err = ice_get_pca9575_handle(hw, &handle);
+ if (err)
+ return err;
+
+ link_topo.handle = CPU_TO_LE16(handle);
+ link_topo.topo_params.node_type_ctx =
+ (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
+ ICE_AQC_LINK_TOPO_NODE_CTX_S);
+
+ addr = CPU_TO_LE16((u16)offset);
+
+ return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);
+}
+
+/**
+ * ice_write_pca9575_reg_e810t
+ * @hw: pointer to the hw struct
+ * @offset: GPIO controller register offset
+ * @data: data to be written to the GPIO controller
+ *
+ * Write the data to the GPIO controller register
+ */
+int
+ice_write_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 data)
+{
+ struct ice_aqc_link_topo_addr link_topo;
+ __le16 addr;
+ int status;
+ u16 handle;
+
+ memset(&link_topo, 0, sizeof(link_topo));
+
+ status = ice_get_pca9575_handle(hw, &handle);
+ if (status)
+ return status;
+
+ link_topo.handle = CPU_TO_LE16(handle);
+ link_topo.topo_params.node_type_ctx =
+ (ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<
+ ICE_AQC_LINK_TOPO_NODE_CTX_S);
+
+ addr = CPU_TO_LE16((u16)offset);
+
+ return ice_aq_write_i2c(hw, link_topo, 0, addr, 1, &data, NULL);
+}
+
/**
* ice_is_pca9575_present
* @hw: pointer to the hw struct
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index 04556db7e9..da5acf7556 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -530,6 +530,10 @@ int ice_ptp_init_phy_cfg(struct ice_hw *hw);
#define E830_HIGH_TX_MEMORY_BANK(slot, port) \
(E830_PRTTSYN_TXTIME_H(slot) + 0x8 * (port))
+#define ICE_SMA_MIN_BIT_E810T 3
+#define ICE_SMA_MAX_BIT_E810T 7
+#define ICE_PCA9575_P1_OFFSET 8
+
/* E810T PCA9575 IO controller registers */
#define ICE_PCA9575_P0_IN 0x0
#define ICE_PCA9575_P1_IN 0x1
@@ -546,9 +550,6 @@ int ice_ptp_init_phy_cfg(struct ice_hw *hw);
#define ICE_E810T_P1_SMA2_DIR_EN BIT(6)
#define ICE_E810T_P1_SMA2_TX_EN BIT(7)
-#define ICE_E810T_SMA_MIN_BIT 3
-#define ICE_E810T_SMA_MAX_BIT 7
-#define ICE_E810T_P1_OFFSET 8
/* 56G PHY quad register base addresses */
#define ICE_PHY0_BASE 0x092000
#define ICE_PHY1_BASE 0x126000
--
2.43.0
