From: Kiran Kumar K <kirankum...@marvell.com>
This patch reserves 2 bits as input selection to select Inner and
outer layers for RSS computation. It is combined with existing
ETH_RSS_* to choose Inner or outer layers for L2, L3 and L4.
This functionality already exists in rte_flow through level parameter in
RSS action configuration rte_flow_action_rss.
Signed-off-by: Kiran Kumar K <kirankum...@marvell.com>
---
lib/librte_ethdev/rte_ethdev.h | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h
index d29930fd8..2164d2f8c 100644
--- a/lib/librte_ethdev/rte_ethdev.h
+++ b/lib/librte_ethdev/rte_ethdev.h
@@ -552,6 +552,33 @@ struct rte_eth_rss_conf {
#define RTE_ETH_RSS_L3_PRE64 (1ULL << 53)
#define RTE_ETH_RSS_L3_PRE96 (1ULL << 52)
+/*
+ * We use the following macros to combine with the above layers to choose
+ * inner and outer layers or both for RSS computation.
+ * Note: Default is 0: inner layers, 1: outer layers, 2: both
+ * bit 56 and 57 are reserved for this.
+ */
+
+/**
+ * Level 0, It basically stands for the innermost encapsulation level RSS
+ * can be performed on according to PMD and device capabilities.
+ */
+#define ETH_RSS_LEVEL_INNER (0ULL << 56)
+/**
+ * Level 1, It basically stands for the outermost encapsulation level RSS
+ * can be performed on according to PMD and device capabilities.
+ */
+#define ETH_RSS_LEVEL_OUTER (1ULL << 56)
+/**
+ * Level 2, It basically stands for the both inner and outermost
+ * encapsulation level RSS can be performed on according to PMD and
+ * device capabilities.
+ */
+#define ETH_RSS_LEVEL_INNER_OUTER (2ULL << 56)
+#define ETH_RSS_LEVEL_MASK (3ULL << 56)
+
+#define ETH_RSS_LEVEL(rss_hf) ((rss_hf & ETH_RSS_LEVEL_MASK) >> 56)
+
/**
* For input set change of hash filter, if SRC_ONLY and DST_ONLY of
* the same level are used simultaneously, it is the same case as
--
2.25.1
