On Thu, 16 May 2019 13:46:58 +0200
Jakub Grajciar <jgraj...@cisco.com> wrote:
> +struct memif_queue {
> + struct rte_mempool *mempool; /**< mempool for RX packets */
> + uint16_t in_port; /**< port id */
> +
> + struct pmd_internals *pmd; /**< device internals */
> +
> + struct rte_intr_handle intr_handle; /**< interrupt handle */
> +
> + /* ring info */
> + memif_ring_type_t type; /**< ring type */
> + memif_ring_t *ring; /**< pointer to ring */
> + memif_log2_ring_size_t log2_ring_size; /**< log2 of ring size */
> +
> + memif_region_index_t region; /**< shared memory region index
> */
> + memif_region_offset_t ring_offset;
> + /**< ring offset from start of shm region (ring - memif_region.addr) */
> +
> + uint16_t last_head; /**< last ring head */
> + uint16_t last_tail; /**< last ring tail */
> +
> + /* rx/tx info */
> + uint64_t n_pkts; /**< number of rx/tx packets */
> + uint64_t n_bytes; /**< number of rx/tx bytes */
> + uint64_t n_err; /**< number of tx errors */
> +};
> +
The layout of this structure has lots of holes, you might want to rearrange
elements.
struct memif_queue {
struct rte_mempool * mempool; /* 0 8 */
uint16_t in_port; /* 8 2 */
/* XXX 6 bytes hole, try to pack */
struct pmd_internals * pmd; /* 16 8 */
struct rte_intr_handle intr_handle; /* 24 26656 */
/* --- cacheline 416 boundary (26624 bytes) was 56 bytes ago --- */
memif_ring_type_t type; /* 26680 4 */
/* XXX 4 bytes hole, try to pack */
/* --- cacheline 417 boundary (26688 bytes) --- */
memif_ring_t * ring; /* 26688 8 */
memif_log2_ring_size_t log2_ring_size; /* 26696 1 */
/* XXX 1 byte hole, try to pack */
memif_region_index_t region; /* 26698 2 */
memif_region_offset_t ring_offset; /* 26700 4 */
uint16_t last_head; /* 26704 2 */
uint16_t last_tail; /* 26706 2 */
/* XXX 4 bytes hole, try to pack */
uint64_t n_pkts; /* 26712 8 */
uint64_t n_bytes; /* 26720 8 */
uint64_t n_err; /* 26728 8 */
/* size: 26736, cachelines: 418, members: 14 */
/* sum members: 26721, holes: 4, sum holes: 15 */
/* last cacheline: 48 bytes */
};
