18/03/2019 13:58, Dekel Peled: > From previous patch description: "to improve performance on PPC64, > use light weight sync instruction instead of sync instruction." > > Excerpt from IBM doc [1], section "Memory barrier instructions": > "The second form of the sync instruction is light-weight sync, > or lwsync. > This form is used to control ordering for storage accesses to system > memory only. It does not create a memory barrier for accesses to > device memory." > > This patch removes the use of lwsync, so calls to rte_wmb() and > rte_rmb() will provide correct memory barrier to ensure order of > accesses to system memory and device memory. > > [1] https://www.ibm.com/developerworks/systems/articles/powerpc.html > > Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER") > Cc: sta...@dpdk.org > > Signed-off-by: Dekel Peled <dek...@mellanox.com>
Applied, thanks
