22/03/2019 16:30, Pradeep Satyanarayana: > Thomas Monjalon <tho...@monjalon.net> wrote on 03/22/2019 01:49:03 AM: > > 22/03/2019 02:40, Pradeep Satyanarayana: > > > - rte_[rw]mb (general memory barrier) --> should be lwsync > > > > This is what may be discussed. > > The assumption is that the general memory barrier should cover > > all cases (CPU caches, SMP and I/O). > > That's why we think it should "sync" for Power. > > In that case, at a minimum we must de-link rte_smp_[rw]mb from rte_[rw]mb > and retain it as lwsync. Agreed?
I have no clue about what is needed for SMP barrier in Power. As long as it works as expected, no problem. > > > - rte_smp_[rw]mb (SMP memory barrier) -->should be lwsync > > > - rte_io_[rw]mb (I/O memory barrier) --> should be sync > > > - rte_cio_[rw]mb (coherent I/O memory barrier) -->should be sync > > > > > > lwsync is appropriate for cases where CPUs are accessing cacheable > > > memory (i.e. Memory Coherence Required) while the sync instruction > > > should be used in all other cases.
