09/01/2019 11:49, Jerin Jacob Kollanukkaran:
> On Wed, 2019-01-09 at 10:22 +0000, Yongseok Koh wrote:
> > On Jan 9, 2019, at 2:09 AM, Jerin Jacob Kollanukkaran wrote:
> > > I think, I way forward is to add config/arm/arm64_a72_linuxapp_gcc
> > > for meson. This config can be used for all SoC with A72 armv8
> > > implementation and may have sym link to specfific SoC to avoid
> > > confusion to end users.
> >
> > Is config/arm/arm64_a72_linuxapp_gcc valid? Others have
>
> Yes. For cross compiling for A72.
Any cross-compilation with meson requires a config file.
The default Arm cross-compilation is done with
config/arm/arm64_armv8_linuxapp_gcc
which set implementor_id = 'generic'
For native compilation, implementor_id is detected from
/sys/devices/system/cpu/cpu0/regs/identification/midr_el1
So each Arm machine needs 2 things:
- a cross-compilation file
- settings based on implementor_id in config/arm/meson.build
> Having not seperate IMPLEMENTOR ID is a chip design issue.
No I don't think it's a design issue.
If the Arm core has no modification, it does not need to be
specially identified.
> I think it can work around by creating
> config/arm/arm64_<your_soc_name>_linuxapp_gcc
> and build on x86 or arm64 through
>
> meson build --cross-file config/arm/arm64_<your_soc_name>_linuxapp_gcc
No, it is a real A72, so it should work with default settings.
The only issue we have is that the default cache line size for Aarch64
is set to 128 in config/arm/meson.build, and this is wrong.
The default cache line is 64 bits.
This is already overriden for Cavium machines which have 128-bit cache lines.
It may be needed to do the same change for other machines (Qualcomm?)
having Arm core modified to 128-bit cache lines.
The other concern is about running a generic Arm build.
Given 64-bit should be the default, generic builds will have this value.
Is it a big issue for running generic 64-bit build on Cavium machines?
