In config/arm64_armv8_linuxapp_gcc, maximum available cache line size
(128B) in arm64 implementations is set by default for generic config.
However, setting 64B is preferable for meson build in order to support
majority of CPUs which don't have Implementor ID or Part Number programmed
on chip.
Signed-off-by: Yongseok Koh <ys...@mellanox.com>
---
Discussion on the mailing list:
https://mails.dpdk.org/archives/dev/2019-January/122441.html
config/arm/meson.build | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/config/arm/meson.build b/config/arm/meson.build
index dae55d6b26..3af256a5ec 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -47,8 +47,7 @@ flags_common_default = [
flags_generic = [
['RTE_MACHINE', '"armv8a"'],
['RTE_MAX_LCORE', 256],
- ['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_CACHE_LINE_SIZE', 128]]
+ ['RTE_USE_C11_MEM_MODEL', true]]
flags_cavium = [
['RTE_MACHINE', '"thunderx"'],
['RTE_CACHE_LINE_SIZE', 128],
@@ -89,15 +88,19 @@ impl_dpaa2 = ['NXP DPAA2', flags_dpaa2,
machine_args_generic]
dpdk_conf.set('RTE_FORCE_INTRINSICS', 1)
+# In config/arm64_armv8_linuxapp_gcc, maximum available cache line size (128B)
+# in arm64 implementations is set by default for generic config. However,
+# setting 64B is preferable for meson build in order to support majority of
CPUs
+# which don't have Implementor ID or Part Number programmed on chip.
+dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
+
if cc.sizeof('void *') != 8
- dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64)
dpdk_conf.set('RTE_ARCH_ARM', 1)
dpdk_conf.set('RTE_ARCH_ARMv7', 1)
# the minimum architecture supported, armv7-a, needs the following,
# mk/machine/armv7a/rte.vars.mk sets it too
machine_args += '-mfpu=neon'
else
- dpdk_conf.set('RTE_CACHE_LINE_SIZE', 128)
dpdk_conf.set('RTE_ARCH_ARM64', 1)
dpdk_conf.set('RTE_ARCH_64', 1)
--
2.11.0
