configure.ac | 6
exynos/exynos_drm.h | 4
include/drm/drm.h | 12
include/drm/i915_drm.h | 33 +
intel/Makefile.am | 2
intel/intel_bufmgr.h | 7
intel/intel_bufmgr_gem.c | 97 +++-
intel/intel_chipset.h | 68 ++
intel/test_decode.c | 2
nouveau/nouveau.c | 35 +
nouveau/nouveau.h | 3
omap/omap_drm.c | 176 ++++++-
omap/omap_drmif.h | 3
radeon/r600_pci_ids.h | 6
radeon/radeon_surface.c | 93 ++--
tests/modetest/Makefile.am | 3
tests/modetest/buffers.c | 1021 +++++++++++++++++++++++++++++++++++++++++++++
tests/modetest/buffers.h | 45 +
tests/modetest/modetest.c | 445 ++++---------------
xf86drm.c | 31 +
xf86drm.h | 3
21 files changed, 1671 insertions(+), 424 deletions(-)
New commits:
commit d1de6831b9f49b1f450324948b6a4759b3f7ae04
Author: Marek Olšák <mar...@gmail.com>
Date: Sat Aug 11 20:05:24 2012 +0200
configure: bump version for 2.4.38 release
diff --git a/configure.ac b/configure.ac
index 3eaec74..3e2792e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.37],
+ [2.4.38],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit 10481fec55b422843d3f15eef3aa9617ae98843b
Author: Marek Olšák <mar...@gmail.com>
Date: Sat Aug 11 20:02:03 2012 +0200
tests/modetest: fix distcheck
diff --git a/tests/modetest/Makefile.am b/tests/modetest/Makefile.am
index 35754a2..b5ec771 100644
--- a/tests/modetest/Makefile.am
+++ b/tests/modetest/Makefile.am
@@ -8,7 +8,8 @@ noinst_PROGRAMS = \
modetest
modetest_SOURCES = \
- buffers.c modetest.c
+ buffers.c modetest.c buffers.h
+
modetest_LDADD = \
$(top_builddir)/libdrm.la \
$(top_builddir)/libkms/libkms.la \
commit 2607dad20b8dffce96608103def75d26ea0e42b2
Author: Eric Anholt <e...@anholt.net>
Date: Wed Aug 1 16:43:16 2012 -0700
intel: Add a function for the new register read ioctl.
Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 2167e43..8d7f239 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -241,6 +241,9 @@ void drm_intel_decode_set_head_tail(struct drm_intel_decode
*ctx,
void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
void drm_intel_decode(struct drm_intel_decode *ctx);
+int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
+ uint32_t offset,
+ uint64_t *result);
/** @{ Compatibility defines to keep old code building despite the symbol
rename
* from dri_* to drm_intel_*
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index ec64e0a..0ea6260 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2947,6 +2947,24 @@ drm_intel_gem_context_destroy(drm_intel_context *ctx)
free(ctx);
}
+int
+drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
+ uint32_t offset,
+ uint64_t *result)
+{
+ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
+ struct drm_i915_reg_read reg_read;
+ int ret;
+
+ VG_CLEAR(reg_read);
+ reg_read.offset = offset;
+
+ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
+
+ *result = reg_read.val;
+ return ret;
+}
+
/**
* Annotate the given bo for use in aub dumping.
commit 934ea3b32127ea2a4ba5bf14228af6c60d3437b6
Author: Eric Anholt <e...@anholt.net>
Date: Wed Aug 1 16:38:19 2012 -0700
intel: Import updated i915_drm.h.
Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 5c8fabe..7e9e9bd 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -195,6 +195,9 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_GEM_WAIT 0x2c
#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
+#define DRM_I915_GEM_SET_CACHEING 0x2f
+#define DRM_I915_GEM_GET_CACHEING 0x30
+#define DRM_I915_REG_READ 0x31
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE +
DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE +
DRM_I915_FLUSH)
@@ -219,6 +222,8 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE +
DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
+#define DRM_IOCTL_I915_GEM_SET_CACHEING
DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct
drm_i915_gem_cacheing)
+#define DRM_IOCTL_I915_GEM_GET_CACHEING
DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct
drm_i915_gem_cacheing)
#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE +
DRM_I915_GEM_THROTTLE)
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
@@ -241,6 +246,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
+#define DRM_IOCTL_I915_REG_READ DRM_IOWR
(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -690,10 +696,31 @@ struct drm_i915_gem_busy {
/** Handle of the buffer to check for busy */
__u32 handle;
- /** Return busy status (1 if busy, 0 if idle) */
+ /** Return busy status (1 if busy, 0 if idle).
+ * The high word is used to indicate on which rings the object
+ * currently resides:
+ * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
+ */
__u32 busy;
};
+#define I915_CACHEING_NONE 0
+#define I915_CACHEING_CACHED 1
+
+struct drm_i915_gem_cacheing {
+ /**
+ * Handle of the buffer to set/get the cacheing level of. */
+ __u32 handle;
+
+ /**
+ * Cacheing level to apply or return value
+ *
+ * bits0-15 are for generic cacheing control (i.e. the above defined
+ * values). bits16-31 are reserved for platform-specific variations
+ * (e.g. l3$ caching on gen7). */
+ __u32 cacheing;
+};
+
#define I915_TILING_NONE 0
#define I915_TILING_X 1
#define I915_TILING_Y 2
@@ -910,4 +937,8 @@ struct drm_i915_gem_context_destroy {
__u32 pad;
};
+struct drm_i915_reg_read {
+ __u64 offset;
+ __u64 val; /* Return value */
+};
#endif /* _I915_DRM_H_ */
commit 71ebcf4ea372927ba8af425a229c4fa75dc45dd1
Author: Eric Anholt <e...@anholt.net>
Date: Thu Aug 2 11:25:57 2012 -0700
Drop "-Wunsafe-loop-optimizations".
It warns about totally sensible things done in intel_decode.c. I've
never seen this warn do anything useful, and apparently I was the one
to introduce it when I added the giant pile of warning flags back in
2008.
Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
diff --git a/configure.ac b/configure.ac
index 09fed53..3eaec74 100644
--- a/configure.ac
+++ b/configure.ac
@@ -133,7 +133,7 @@ MAYBE_WARN="-Wall -Wextra \
-Wpointer-arith -Wwrite-strings -Wstrict-prototypes \
-Wmissing-prototypes -Wmissing-declarations -Wnested-externs \
-Wpacked -Wswitch-enum -Wmissing-format-attribute \
--Wstrict-aliasing=2 -Winit-self -Wunsafe-loop-optimizations \
+-Wstrict-aliasing=2 -Winit-self \
-Wdeclaration-after-statement -Wold-style-definition \
-Wno-missing-field-initializers -Wno-unused-parameter \
-Wno-attributes -Wno-long-long -Winline"
commit 128803a107fde8ce36036e59437a536fc4d46553
Author: Marek Olšák <mar...@gmail.com>
Date: Tue Aug 7 23:38:19 2012 +0200
radeon: tweak TILE_SPLIT for MSAA surfaces
Reviewed-by: Jerome Glisse <jgli...@redhat.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 499e994..892dca6 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -871,12 +871,37 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
return 0;
}
- /* set tile split to row size, optimize latter for multi-sample surface
- * tile split >= 256 for render buffer surface. Also depth surface want
- * smaller value for optimal performances.
- */
- surf->tile_split = surf_man->hw_info.row_size;
- surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
+ /* Tweak TILE_SPLIT for performance here. */
+ if (surf->nsamples > 1) {
+ if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
+ switch (surf->nsamples) {
+ case 2:
+ surf->tile_split = 128;
+ break;
+ case 4:
+ surf->tile_split = 128;
+ break;
+ case 8:
+ surf->tile_split = 256;
+ break;
+ case 16: /* cayman only */
+ surf->tile_split = 512;
+ break;
+ default:
+ fprintf(stderr, "radeon: Wrong number of samples %i (%i)\n",
+ surf->nsamples, __LINE__);
+ return -EINVAL;
+ }
+ surf->stencil_tile_split = 64;
+ } else {
+ /* tile split must be >= 256 for colorbuffer surfaces */
+ surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
+ }
+ } else {
+ /* set tile split to row size */
+ surf->tile_split = surf_man->hw_info.row_size;
+ surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
+ }
/* bankw or bankh greater than 1 increase alignment requirement, not
* sure if it's worth using smaller bankw & bankh to stick with 2D
commit e14aedce64e365ef1a8726ed8c1ebed881d7a398
Author: Marek Olšák <mar...@gmail.com>
Date: Tue Aug 7 22:50:39 2012 +0200
radeon: force 2D tiling for MSAA surfaces
Reviewed-by: Jerome Glisse <jgli...@redhat.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 874a092..499e994 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -154,7 +154,7 @@ static void surf_minify(struct radeon_surface *surf,
surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1)
/ surf->blk_w;
surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1)
/ surf->blk_h;
surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1)
/ surf->blk_d;
- if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D)
{
if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y <
yalign) {
surf->level[level].mode = RADEON_SURF_MODE_1D;
return;
@@ -382,6 +382,12 @@ static int r6_surface_init(struct radeon_surface_manager
*surf_man,
unsigned mode;
int r;
+ /* MSAA surfaces support the 2D mode only. */
+ if (surf->nsamples > 1) {
+ surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
+ surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ }
+
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
@@ -401,6 +407,10 @@ static int r6_surface_init(struct radeon_surface_manager
*surf_man,
/* force 1d on kernel that can't do 2d */
if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
+ if (surf->nsamples > 1) {
+ fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface
(%i).\n", __LINE__);
+ return -EFAULT;
+ }
mode = RADEON_SURF_MODE_1D;
surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
surf->flags |= RADEON_SURF_SET(mode, MODE);
@@ -548,7 +558,7 @@ static void eg_surf_minify(struct radeon_surface *surf,
surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1)
/ surf->blk_w;
surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1)
/ surf->blk_h;
surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1)
/ surf->blk_d;
- if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D)
{
if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y <
mtileh) {
surf->level[level].mode = RADEON_SURF_MODE_1D;
return;
@@ -687,6 +697,10 @@ static int eg_surface_sanity(struct radeon_surface_manager
*surf_man,
/* force 1d on kernel that can't do 2d */
if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
+ if (surf->nsamples > 1) {
+ fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface
(%i).\n", __LINE__);
+ return -EFAULT;
+ }
mode = RADEON_SURF_MODE_1D;
surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
surf->flags |= RADEON_SURF_SET(mode, MODE);
@@ -754,6 +768,12 @@ static int eg_surface_init(struct radeon_surface_manager
*surf_man,
unsigned mode;
int r;
+ /* MSAA surfaces support the 2D mode only. */
+ if (surf->nsamples > 1) {
+ surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
+ surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ }
+
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
commit 23372955730048bbcddafc74365d911f9a74fb13
Author: Marek Olšák <mar...@gmail.com>
Date: Sun Jul 29 15:20:15 2012 +0200
radeon: optimize allocation for depth w/o stencil and stencil w/o depth on
EG
If we don't need stencil, don't allocate it.
If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.
v2: actually do it correctly
Reviewed-by: Christian König <christian.koe...@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 5800c33..874a092 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -604,7 +604,11 @@ static int eg_surface_init_1d(struct
radeon_surface_manager *surf_man,
}
}
- if (surf->flags & RADEON_SURF_SBUFFER) {
+ /* The depth and stencil buffers are in separate resources on evergreen.
+ * We allocate them in one buffer next to each other to simplify
+ * communication between the DDX and the Mesa driver. */
+ if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
+ (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
}
@@ -656,7 +660,8 @@ static int eg_surface_init_2d(struct radeon_surface_manager
*surf_man,
}
}
- if (surf->flags & RADEON_SURF_SBUFFER) {
+ if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
+ (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
}
@@ -752,14 +757,7 @@ static int eg_surface_init(struct radeon_surface_manager
*surf_man,
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
- /* for some reason eg need to have room for stencil right after depth */
- if (surf->flags & RADEON_SURF_ZBUFFER) {
- surf->flags |= RADEON_SURF_SBUFFER;
- }
- if (surf->flags & RADEON_SURF_SBUFFER) {
- surf->flags |= RADEON_SURF_ZBUFFER;
- }
- if (surf->flags & RADEON_SURF_ZBUFFER) {
+ if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
/* zbuffer only support 1D or 2D tiled surface */
switch (mode) {
case RADEON_SURF_MODE_1D:
@@ -828,11 +826,6 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
- /* for some reason eg need to have room for stencil right after depth */
- if (surf->flags & RADEON_SURF_ZBUFFER) {
- surf->flags |= RADEON_SURF_SBUFFER;
- }
-
/* set some default value to avoid sanity check choking on them */
surf->tile_split = 1024;
surf->bankw = 1;
commit ad66c17209811acdae21e44290a449523882a734
Author: Marek Olšák <mar...@gmail.com>
Date: Sun Jul 29 14:10:07 2012 +0200
radeon: simplify ZS buffer checking on r600
Setting those flags has no effect anywhere else.
Reviewed-by: Christian König <christian.koe...@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index c80f7f4..5800c33 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -385,14 +385,7 @@ static int r6_surface_init(struct radeon_surface_manager
*surf_man,
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
- /* always enable z & stencil together */
- if (surf->flags & RADEON_SURF_ZBUFFER) {
- surf->flags |= RADEON_SURF_SBUFFER;
- }
- if (surf->flags & RADEON_SURF_SBUFFER) {
- surf->flags |= RADEON_SURF_ZBUFFER;
- }
- if (surf->flags & RADEON_SURF_ZBUFFER) {
+ if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
/* zbuffer only support 1D or 2D tiled surface */
switch (mode) {
case RADEON_SURF_MODE_1D:
commit 93fef04b1e3a83e2f884880ed1c3395f67b038ab
Author: Paulo Zanoni <paulo.r.zan...@intel.com>
Date: Mon Aug 6 14:55:23 2012 -0300
intel: add more Haswell PCI IDs
Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@gmail.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 9c1abc8..b73fa0f 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -48,9 +48,40 @@
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
+#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */
+#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
+#define PCI_CHIP_HASWELL_S_GT2 0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
+#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
+#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
+#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
+#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
+#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
+#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
+#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
+#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
+#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
+#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
+#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
+#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
+#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
+#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
+#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
+#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
+#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
+#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
+#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
+#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
#define IS_830(dev) (dev == 0x3577)
#define IS_845(dev) (dev == 0x2562)
@@ -133,10 +164,41 @@
dev == PCI_CHIP_IVYBRIDGE_S_GT2)
#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
- devid == PCI_CHIP_HASWELL_M_GT1)
+ devid == PCI_CHIP_HASWELL_M_GT1 || \
+ devid == PCI_CHIP_HASWELL_S_GT1 || \
+ devid == PCI_CHIP_HASWELL_SDV_GT1 || \
+ devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
+ devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
+ devid == PCI_CHIP_HASWELL_ULT_GT1 || \
+ devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
+ devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
+ devid == PCI_CHIP_HASWELL_CRW_GT1 || \
+ devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
+ devid == PCI_CHIP_HASWELL_CRW_S_GT1)
#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \
devid == PCI_CHIP_HASWELL_M_GT2 || \
- devid == PCI_CHIP_HASWELL_M_ULT_GT2)
+ devid == PCI_CHIP_HASWELL_S_GT2 || \
+ devid == PCI_CHIP_HASWELL_SDV_GT2 || \
+ devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
+ devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
+ devid == PCI_CHIP_HASWELL_ULT_GT2 || \
+ devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
+ devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+ devid == PCI_CHIP_HASWELL_CRW_GT2 || \
+ devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
+ devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+ devid == PCI_CHIP_HASWELL_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
+ devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
IS_HSW_GT2(devid))
commit 9a2b57d229fe3e6a1c9799e8cd5397969202d223
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Wed Jul 25 16:28:59 2012 +0100
intel: Bail gracefully if we encounter an unknown Intel device
Otherwise we end up with X hitting a fail-loop as the embedded libGL
stacks asserts whilst initialising.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index a484b12..ec64e0a 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3044,9 +3044,11 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
else if (IS_GEN6(bufmgr_gem->pci_device))
bufmgr_gem->gen = 6;
else if (IS_GEN7(bufmgr_gem->pci_device))
- bufmgr_gem->gen = 7;
- else
- assert(0);
+ bufmgr_gem->gen = 7;
+ else {
+ free(bufmgr_gem);
+ return NULL;
+ }
if (IS_GEN3(bufmgr_gem->pci_device) &&
bufmgr_gem->gtt_size > 256*1024*1024) {
commit 9f823ca236058d7eb37d54a077170fff2d691b99
Author: Alex Deucher <alexander.deuc...@amd.com>
Date: Mon Aug 6 10:32:19 2012 -0400
radeon: add some new SI pci ids
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 2aaf35b..12daafd 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -327,9 +327,12 @@ CHIPSET(0x679F, TAHITI_679F, TAHITI)
CHIPSET(0x6800, PITCAIRN_6800, PITCAIRN)
CHIPSET(0x6801, PITCAIRN_6801, PITCAIRN)
CHIPSET(0x6802, PITCAIRN_6802, PITCAIRN)
+CHIPSET(0x6806, PITCAIRN_6806, PITCAIRN)
CHIPSET(0x6808, PITCAIRN_6808, PITCAIRN)
CHIPSET(0x6809, PITCAIRN_6809, PITCAIRN)
CHIPSET(0x6810, PITCAIRN_6810, PITCAIRN)
+CHIPSET(0x6816, PITCAIRN_6816, PITCAIRN)
+CHIPSET(0x6817, PITCAIRN_6817, PITCAIRN)
CHIPSET(0x6818, PITCAIRN_6818, PITCAIRN)
CHIPSET(0x6819, PITCAIRN_6819, PITCAIRN)
CHIPSET(0x684C, PITCAIRN_684C, PITCAIRN)
commit dd944a00815c38af1e7424f67bf71ffb90deceb1
Author: Alex Deucher <alexander.deuc...@amd.com>
Date: Mon Aug 6 10:29:24 2012 -0400
radeon: add some missing evergreen pci ids
Noticed by: Harald van Dijk <f...@gigawatt.nl>
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=53124
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 989ec00..2aaf35b 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -157,6 +157,7 @@ CHIPSET(0x68FE, CEDAR_68FE, CEDAR)
CHIPSET(0x68C0, REDWOOD_68C0, REDWOOD)
CHIPSET(0x68C1, REDWOOD_68C1, REDWOOD)
+CHIPSET(0x68C7, REDWOOD_68C7, REDWOOD)
CHIPSET(0x68C8, REDWOOD_68C8, REDWOOD)
CHIPSET(0x68C9, REDWOOD_68C9, REDWOOD)
CHIPSET(0x68D8, REDWOOD_68D8, REDWOOD)
@@ -179,6 +180,8 @@ CHIPSET(0x6880, CYPRESS_6880, CYPRESS)
CHIPSET(0x6888, CYPRESS_6888, CYPRESS)
CHIPSET(0x6889, CYPRESS_6889, CYPRESS)
CHIPSET(0x688A, CYPRESS_688A, CYPRESS)
+CHIPSET(0x688C, CYPRESS_688C, CYPRESS)
+CHIPSET(0x688D, CYPRESS_688D, CYPRESS)
CHIPSET(0x6898, CYPRESS_6898, CYPRESS)
CHIPSET(0x6899, CYPRESS_6899, CYPRESS)
CHIPSET(0x689B, CYPRESS_689B, CYPRESS)
commit 7e3f08b463bcbae6950c07cc9ea29a7057f28e69
Author: Eric Anholt <e...@anholt.net>
Date: Wed Jul 18 13:45:14 2012 -0700
intel: Quiet valgrind warnings in context creation.
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 43c49a9..a484b12 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2911,6 +2911,7 @@ drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
drm_intel_context *context = NULL;
int ret;
+ VG_CLEAR(create);
ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE,
&create);
if (ret != 0) {
DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n",
commit c10b08d95954aecd331e5a43b4861c6c04b8aadd
Author: Damien Lespiau <damien.lesp...@intel.com>
Date: Thu Jul 26 17:50:09 2012 +0100
intel: Remove two unused variables
Signed-off-by: Damien Lespiau <damien.lesp...@intel.com>
Reviewed-by: Eric Anholt <e...@anholt.net>
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index eae2199..43c49a9 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2908,9 +2908,8 @@ drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
struct drm_i915_gem_context_create create;
- drm_i915_getparam_t gp;
drm_intel_context *context = NULL;
- int tmp = 0, ret;
+ int ret;
ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CONTEXT_CREATE,
&create);
if (ret != 0) {
commit ebd7904877d08525beb5039e4ea2f5b6c0a7c23f
Author: Rob Clark <r...@ti.com>
Date: Mon Jul 23 11:35:06 2012 -0500
modetest: fix uninitialized fourcc
If color format for CRTC layer is not specified on commandline, then
c->fourcc is unintialized resulting in addfb call failing.
Signed-off-by: Rob Clark <r...@ti.com>
diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c
index 3e74008..e0fd66c 100644
--- a/tests/modetest/modetest.c
+++ b/tests/modetest/modetest.c
@@ -867,12 +867,12 @@ static int parse_connector(struct connector *c, const
char *arg)
if (*p == '@') {
strncpy(c->format_str, p + 1, 4);
c->format_str[4] = '\0';
+ }
- c->fourcc = format_fourcc(p + 1);
- if (c->fourcc == 0) {
- fprintf(stderr, "unknown format %s\n", c->format_str);
- return -1;
- }
+ c->fourcc = format_fourcc(c->format_str);
+ if (c->fourcc == 0) {
+ fprintf(stderr, "unknown format %s\n", c->format_str);
+ return -1;
}
return 0;
commit db004badef9315ba6a5f165d0974dd5afd5a6178
Author: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
Date: Fri Jul 20 16:37:00 2012 +0200
modeset: Split buffer allocation to a separate file
As the modeset test application is often referred to as an example of
the KMS API usage, move test pattern generation and buffer allocation to
a separate file to keep it simple and clear.
Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
diff --git a/tests/modetest/Makefile.am b/tests/modetest/Makefile.am
index 2191242..35754a2 100644
--- a/tests/modetest/Makefile.am
+++ b/tests/modetest/Makefile.am
@@ -8,7 +8,7 @@ noinst_PROGRAMS = \
modetest
modetest_SOURCES = \
- modetest.c
+ buffers.c modetest.c
modetest_LDADD = \
$(top_builddir)/libdrm.la \
$(top_builddir)/libkms/libkms.la \
diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c
new file mode 100644
index 0000000..5086381
--- /dev/null
+++ b/tests/modetest/buffers.c
@@ -0,0 +1,1021 @@
+/*
+ * DRM based mode setting test program
+ * Copyright 2008 Tungsten Graphics
+ * Jakob Bornecrantz <ja...@tungstengraphics.com>
+ * Copyright 2008 Intel Corporation
+ * Jesse Barnes <jesse.bar...@intel.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "config.h"
+
+#include <assert.h>
+#include <errno.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "drm_fourcc.h"
+#include "libkms.h"
+
+#include "buffers.h"
+
+#ifdef HAVE_CAIRO
+#include <math.h>
+#include <cairo.h>
+#endif
+
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
+
+/*
-----------------------------------------------------------------------------
+ * Formats
+ */
+
+struct color_component {
+ unsigned int length;
+ unsigned int offset;
+};
+
+struct rgb_info {
+ struct color_component red;
+ struct color_component green;
+ struct color_component blue;
+ struct color_component alpha;
+};
+
+enum yuv_order {
+ YUV_YCbCr = 1,
+ YUV_YCrCb = 2,
+ YUV_YC = 4,
+ YUV_CY = 8,
+};
+
+struct yuv_info {
+ enum yuv_order order;
+ unsigned int xsub;
+ unsigned int ysub;
+ unsigned int chroma_stride;
+};
+
+struct format_info {
+ unsigned int format;
+ const char *name;
+ const struct rgb_info rgb;
+ const struct yuv_info yuv;
+};
+
+#define MAKE_RGB_INFO(rl, ro, bl, bo, gl, go, al, ao) \
+ .rgb = { { (rl), (ro) }, { (bl), (bo) }, { (gl), (go) }, { (al), (ao) }
}
+
+#define MAKE_YUV_INFO(order, xsub, ysub, chroma_stride) \
+ .yuv = { (order), (xsub), (ysub), (chroma_stride) }
+
+static const struct format_info format_info[] = {
+ /* YUV packed */
+ { DRM_FORMAT_UYVY, "UYVY", MAKE_YUV_INFO(YUV_YCbCr | YUV_CY, 2, 2, 2) },
+ { DRM_FORMAT_VYUY, "VYUY", MAKE_YUV_INFO(YUV_YCrCb | YUV_CY, 2, 2, 2) },
+ { DRM_FORMAT_YUYV, "YUYV", MAKE_YUV_INFO(YUV_YCbCr | YUV_YC, 2, 2, 2) },
+ { DRM_FORMAT_YVYU, "YVYU", MAKE_YUV_INFO(YUV_YCrCb | YUV_YC, 2, 2, 2) },
+ /* YUV semi-planar */
+ { DRM_FORMAT_NV12, "NV12", MAKE_YUV_INFO(YUV_YCbCr, 2, 2, 2) },
+ { DRM_FORMAT_NV21, "NV21", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 2) },
+ { DRM_FORMAT_NV16, "NV16", MAKE_YUV_INFO(YUV_YCbCr, 2, 1, 2) },
+ { DRM_FORMAT_NV61, "NV61", MAKE_YUV_INFO(YUV_YCrCb, 2, 1, 2) },
+ /* YUV planar */
+ { DRM_FORMAT_YVU420, "YV12", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 1) },
+ /* RGB16 */
+ { DRM_FORMAT_ARGB1555, "AR15", MAKE_RGB_INFO(5, 10, 5, 5, 5, 0, 1, 15)
},
+ { DRM_FORMAT_XRGB1555, "XR15", MAKE_RGB_INFO(5, 10, 5, 5, 5, 0, 0, 0) },
+ { DRM_FORMAT_RGB565, "RG16", MAKE_RGB_INFO(5, 11, 6, 5, 5, 0, 0, 0) },
+ /* RGB24 */
+ { DRM_FORMAT_BGR888, "BG24", MAKE_RGB_INFO(8, 0, 8, 8, 8, 16, 0, 0) },
+ { DRM_FORMAT_RGB888, "RG24", MAKE_RGB_INFO(8, 16, 8, 8, 8, 0, 0, 0) },
+ /* RGB32 */
+ { DRM_FORMAT_ARGB8888, "AR24", MAKE_RGB_INFO(8, 16, 8, 8, 8, 0, 8, 24)
},
+ { DRM_FORMAT_BGRA8888, "BA24", MAKE_RGB_INFO(8, 8, 8, 16, 8, 24, 8, 0)
},
+ { DRM_FORMAT_XRGB8888, "XR24", MAKE_RGB_INFO(8, 16, 8, 8, 8, 0, 0, 0) },
+ { DRM_FORMAT_BGRX8888, "BX24", MAKE_RGB_INFO(8, 8, 8, 16, 8, 24, 0, 0)
},
+};
+
+unsigned int format_fourcc(const char *name)
+{
+ unsigned int i;
+ for (i = 0; i < ARRAY_SIZE(format_info); i++) {
+ if (!strcmp(format_info[i].name, name))
+ return format_info[i].format;
+ }
+ return 0;
+}
+
+/*
-----------------------------------------------------------------------------
+ * Test patterns
+ */
+
+struct color_rgb24 {
+ unsigned int value:24;
+} __attribute__((__packed__));
+
+struct color_yuv {
+ unsigned char y;
+ unsigned char u;
+ unsigned char v;
+};
+
+#define MAKE_YUV_601_Y(r, g, b) \
+ ((( 66 * (r) + 129 * (g) + 25 * (b) + 128) >> 8) + 16)
+#define MAKE_YUV_601_U(r, g, b) \
+ (((-38 * (r) - 74 * (g) + 112 * (b) + 128) >> 8) + 128)
+#define MAKE_YUV_601_V(r, g, b) \
+ (((112 * (r) - 94 * (g) - 18 * (b) + 128) >> 8) + 128)
+
+#define MAKE_YUV_601(r, g, b) \
+ { .y = MAKE_YUV_601_Y(r, g, b), \
+ .u = MAKE_YUV_601_U(r, g, b), \
+ .v = MAKE_YUV_601_V(r, g, b) }
+
+#define MAKE_RGBA(rgb, r, g, b, a) \
+ ((((r) >> (8 - (rgb)->red.length)) << (rgb)->red.offset) | \
+ (((g) >> (8 - (rgb)->green.length)) << (rgb)->green.offset) | \
+ (((b) >> (8 - (rgb)->blue.length)) << (rgb)->blue.offset) | \
+ (((a) >> (8 - (rgb)->alpha.length)) << (rgb)->alpha.offset))
+
+#define MAKE_RGB24(rgb, r, g, b) \
+ { .value = MAKE_RGBA(rgb, r, g, b, 0) }
+
+static void
+fill_smpte_yuv_planar(const struct yuv_info *yuv,
+ unsigned char *y_mem, unsigned char *u_mem,
+ unsigned char *v_mem, unsigned int width,
+ unsigned int height, unsigned int stride)
+{
+ const struct color_yuv colors_top[] = {
+ MAKE_YUV_601(191, 192, 192), /* grey */
+ MAKE_YUV_601(192, 192, 0), /* yellow */
+ MAKE_YUV_601(0, 192, 192), /* cyan */
+ MAKE_YUV_601(0, 192, 0), /* green */
+ MAKE_YUV_601(192, 0, 192), /* magenta */
+ MAKE_YUV_601(192, 0, 0), /* red */
+ MAKE_YUV_601(0, 0, 192), /* blue */
+ };
+ const struct color_yuv colors_middle[] = {
+ MAKE_YUV_601(0, 0, 192), /* blue */
+ MAKE_YUV_601(19, 19, 19), /* black */
+ MAKE_YUV_601(192, 0, 192), /* magenta */
+ MAKE_YUV_601(19, 19, 19), /* black */
+ MAKE_YUV_601(0, 192, 192), /* cyan */
+ MAKE_YUV_601(19, 19, 19), /* black */
+ MAKE_YUV_601(192, 192, 192), /* grey */
+ };
+ const struct color_yuv colors_bottom[] = {
+ MAKE_YUV_601(0, 33, 76), /* in-phase */
+ MAKE_YUV_601(255, 255, 255), /* super white */
+ MAKE_YUV_601(50, 0, 106), /* quadrature */
+ MAKE_YUV_601(19, 19, 19), /* black */
+ MAKE_YUV_601(9, 9, 9), /* 3.5% */
+ MAKE_YUV_601(19, 19, 19), /* 7.5% */
+ MAKE_YUV_601(29, 29, 29), /* 11.5% */
+ MAKE_YUV_601(19, 19, 19), /* black */
+ };
+ unsigned int cs = yuv->chroma_stride;
+ unsigned int xsub = yuv->xsub;
+ unsigned int ysub = yuv->ysub;
+ unsigned int x;
+ unsigned int y;
+
+ /* Luma */
+ for (y = 0; y < height * 6 / 9; ++y) {
+ for (x = 0; x < width; ++x)
+ y_mem[x] = colors_top[x * 7 / width].y;
+ y_mem += stride;
+ }
+
+ for (; y < height * 7 / 9; ++y) {
+ for (x = 0; x < width; ++x)
+ y_mem[x] = colors_middle[x * 7 / width].y;
+ y_mem += stride;
+ }
+
+ for (; y < height; ++y) {
+ for (x = 0; x < width * 5 / 7; ++x)
+ y_mem[x] = colors_bottom[x * 4 / (width * 5 / 7)].y;
+ for (; x < width * 6 / 7; ++x)
+ y_mem[x] = colors_bottom[(x - width * 5 / 7) * 3
+ / (width / 7) + 4].y;
+ for (; x < width; ++x)
+ y_mem[x] = colors_bottom[7].y;
+ y_mem += stride;
+ }
+
+ /* Chroma */
+ for (y = 0; y < height / ysub * 6 / 9; ++y) {
+ for (x = 0; x < width; x += xsub) {
+ u_mem[x*cs/xsub] = colors_top[x * 7 / width].u;
+ v_mem[x*cs/xsub] = colors_top[x * 7 / width].v;
+ }
+ u_mem += stride * cs / xsub;
+ v_mem += stride * cs / xsub;
+ }
+
--
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