ChangeLog | 397 +++++++++++++++
configure.ac | 6
debian/changelog | 2
debian/libdrm-intel1.symbols | 3
debian/libdrm-nouveau2.symbols | 2
debian/libdrm-omap1.symbols | 3
debian/libdrm2.symbols | 2
exynos/exynos_drm.h | 4
include/drm/drm.h | 12
include/drm/i915_drm.h | 33 +
intel/Makefile.am | 2
intel/intel_bufmgr.h | 7
intel/intel_bufmgr_gem.c | 97 +++
intel/intel_chipset.h | 68 ++
intel/test_decode.c | 2
nouveau/nouveau.c | 35 +
nouveau/nouveau.h | 3
omap/omap_drm.c | 176 ++++++-
omap/omap_drmif.h | 3
radeon/r600_pci_ids.h | 6
radeon/radeon_surface.c | 93 ++-
tests/modetest/Makefile.am | 3
tests/modetest/buffers.c | 1021 +++++++++++++++++++++++++++++++++++++++++
tests/modetest/buffers.h | 45 +
tests/modetest/modetest.c | 445 +++--------------
xf86drm.c | 31 +
xf86drm.h | 3
27 files changed, 2079 insertions(+), 425 deletions(-)
New commits:
commit 0061694cb071e8a9a476a0f02c1c2563137bc543
Author: Maarten Lankhorst <maarten.lankho...@canonical.com>
Date: Mon Aug 13 10:52:29 2012 +0200
Add new symbols for 2.4.38
diff --git a/debian/libdrm-intel1.symbols b/debian/libdrm-intel1.symbols
index 21887ca..8f5b9fe 100644
--- a/debian/libdrm-intel1.symbols
+++ b/debian/libdrm-intel1.symbols
@@ -11,6 +11,8 @@ libdrm_intel.so.1 libdrm-intel1 #MINVER#
drm_intel_bo_fake_disable_backing_store@Base 2.4.1
drm_intel_bo_flink@Base 2.4.1
drm_intel_bo_gem_create_from_name@Base 2.4.1
+ drm_intel_bo_gem_create_from_prime@Base 2.4.38
+ drm_intel_bo_gem_export_to_prime@Base 2.4.38
drm_intel_bo_get_subdata@Base 2.4.1
drm_intel_bo_get_tiling@Base 2.4.1
drm_intel_bo_is_reusable@Base 2.4.21
@@ -62,6 +64,7 @@ libdrm_intel.so.1 libdrm-intel1 #MINVER#
drm_intel_gem_context_destroy@Base 2.4.37
drm_intel_get_aperture_sizes@Base 2.4.26
drm_intel_get_pipe_from_crtc_id@Base 2.4.11
+ drm_intel_reg_read@Base 2.4.38
drm_mmAllocMem@Base 2.4.1
drm_mmDestroy@Base 2.4.1
drm_mmDumpMemInfo@Base 2.4.1
diff --git a/debian/libdrm-nouveau2.symbols b/debian/libdrm-nouveau2.symbols
index 4433983..8fbd8a9 100644
--- a/debian/libdrm-nouveau2.symbols
+++ b/debian/libdrm-nouveau2.symbols
@@ -9,7 +9,9 @@ libdrm_nouveau.so.2 libdrm-nouveau2 #MINVER#
nouveau_bo_name_get@Base 2.4.34
nouveau_bo_name_ref@Base 2.4.34
nouveau_bo_new@Base 2.4.34
+ nouveau_bo_prime_handle_ref@Base 2.4.38
nouveau_bo_ref@Base 2.4.34
+ nouveau_bo_set_prime@Base 2.4.38
nouveau_bo_wait@Base 2.4.34
nouveau_bo_wrap@Base 2.4.34
nouveau_bufctx_del@Base 2.4.34
diff --git a/debian/libdrm-omap1.symbols b/debian/libdrm-omap1.symbols
index c15e79c..0c12475 100644
--- a/debian/libdrm-omap1.symbols
+++ b/debian/libdrm-omap1.symbols
@@ -3,14 +3,17 @@ libdrm_omap.so.1 libdrm-omap1 #MINVER#
omap_bo_cpu_prep@Base 2.4.33
omap_bo_del@Base 2.4.33
omap_bo_dmabuf@Base 2.4.34
+ omap_bo_from_dmabuf@Base 2.4.38
omap_bo_from_name@Base 2.4.33
omap_bo_get_name@Base 2.4.33
omap_bo_handle@Base 2.4.33
omap_bo_map@Base 2.4.33
omap_bo_new@Base 2.4.33
omap_bo_new_tiled@Base 2.4.33
+ omap_bo_ref@Base 2.4.38
omap_bo_size@Base 2.4.33
omap_device_del@Base 2.4.33
omap_device_new@Base 2.4.33
+ omap_device_ref@Base 2.4.38
omap_get_param@Base 2.4.33
omap_set_param@Base 2.4.33
diff --git a/debian/libdrm2.symbols b/debian/libdrm2.symbols
index 84f5462..c4047c4 100644
--- a/debian/libdrm2.symbols
+++ b/debian/libdrm2.symbols
@@ -116,6 +116,8 @@ libdrm.so.2 libdrm2 #MINVER#
drmOpen@Base 2.3.1
drmOpenControl@Base 2.4.3
drmOpenOnce@Base 2.3.1
+ drmPrimeFDToHandle@Base 2.4.38
+ drmPrimeHandleToFD@Base 2.4.38
drmRandom@Base 2.3.1
drmRandomCreate@Base 2.3.1
drmRandomDestroy@Base 2.3.1
commit 70a0cfaab587afe4377456f27e37baa546dbc48b
Author: Maarten Lankhorst <maarten.lankho...@canonical.com>
Date: Mon Aug 13 10:37:22 2012 +0200
New upstream release
diff --git a/ChangeLog b/ChangeLog
index 41ed7c5..b8e9743 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,400 @@
+commit d1de6831b9f49b1f450324948b6a4759b3f7ae04
+Author: Marek Olšák <mar...@gmail.com>
+Date: Sat Aug 11 20:05:24 2012 +0200
+
+ configure: bump version for 2.4.38 release
+
+commit 10481fec55b422843d3f15eef3aa9617ae98843b
+Author: Marek Olšák <mar...@gmail.com>
+Date: Sat Aug 11 20:02:03 2012 +0200
+
+ tests/modetest: fix distcheck
+
+commit 2607dad20b8dffce96608103def75d26ea0e42b2
+Author: Eric Anholt <e...@anholt.net>
+Date: Wed Aug 1 16:43:16 2012 -0700
+
+ intel: Add a function for the new register read ioctl.
+
+ Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
+
+commit 934ea3b32127ea2a4ba5bf14228af6c60d3437b6
+Author: Eric Anholt <e...@anholt.net>
+Date: Wed Aug 1 16:38:19 2012 -0700
+
+ intel: Import updated i915_drm.h.
+
+ Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
+
+commit 71ebcf4ea372927ba8af425a229c4fa75dc45dd1
+Author: Eric Anholt <e...@anholt.net>
+Date: Thu Aug 2 11:25:57 2012 -0700
+
+ Drop "-Wunsafe-loop-optimizations".
+
+ It warns about totally sensible things done in intel_decode.c. I've
+ never seen this warn do anything useful, and apparently I was the one
+ to introduce it when I added the giant pile of warning flags back in
+ 2008.
+
+ Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
+
+commit 128803a107fde8ce36036e59437a536fc4d46553
+Author: Marek Olšák <mar...@gmail.com>
+Date: Tue Aug 7 23:38:19 2012 +0200
+
+ radeon: tweak TILE_SPLIT for MSAA surfaces
+
+ Reviewed-by: Jerome Glisse <jgli...@redhat.com>
+
+commit e14aedce64e365ef1a8726ed8c1ebed881d7a398
+Author: Marek Olšák <mar...@gmail.com>
+Date: Tue Aug 7 22:50:39 2012 +0200
+
+ radeon: force 2D tiling for MSAA surfaces
+
+ Reviewed-by: Jerome Glisse <jgli...@redhat.com>
+
+commit 23372955730048bbcddafc74365d911f9a74fb13
+Author: Marek Olšák <mar...@gmail.com>
+Date: Sun Jul 29 15:20:15 2012 +0200
+
+ radeon: optimize allocation for depth w/o stencil and stencil w/o depth on
EG
+
+ If we don't need stencil, don't allocate it.
+ If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.
+
+ v2: actually do it correctly
+
+ Reviewed-by: Christian König <christian.koe...@amd.com>
+
+commit ad66c17209811acdae21e44290a449523882a734
+Author: Marek Olšák <mar...@gmail.com>
+Date: Sun Jul 29 14:10:07 2012 +0200
+
+ radeon: simplify ZS buffer checking on r600
+
+ Setting those flags has no effect anywhere else.
+
+ Reviewed-by: Christian König <christian.koe...@amd.com>
+
+commit 93fef04b1e3a83e2f884880ed1c3395f67b038ab
+Author: Paulo Zanoni <paulo.r.zan...@intel.com>
+Date: Mon Aug 6 14:55:23 2012 -0300
+
+ intel: add more Haswell PCI IDs
+
+ Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
+ Reviewed-by: Rodrigo Vivi <rodrigo.v...@gmail.com>
+
+commit 9a2b57d229fe3e6a1c9799e8cd5397969202d223
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Wed Jul 25 16:28:59 2012 +0100
+
+ intel: Bail gracefully if we encounter an unknown Intel device
+
+ Otherwise we end up with X hitting a fail-loop as the embedded libGL
+ stacks asserts whilst initialising.
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+
+commit 9f823ca236058d7eb37d54a077170fff2d691b99
+Author: Alex Deucher <alexander.deuc...@amd.com>
+Date: Mon Aug 6 10:32:19 2012 -0400
+
+ radeon: add some new SI pci ids
+
+ Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
+
+commit dd944a00815c38af1e7424f67bf71ffb90deceb1
+Author: Alex Deucher <alexander.deuc...@amd.com>
+Date: Mon Aug 6 10:29:24 2012 -0400
+
+ radeon: add some missing evergreen pci ids
+
+ Noticed by: Harald van Dijk <f...@gigawatt.nl>
+
+ Fixes:
+ https://bugs.freedesktop.org/show_bug.cgi?id=53124
+
+ Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
+
+commit 7e3f08b463bcbae6950c07cc9ea29a7057f28e69
+Author: Eric Anholt <e...@anholt.net>
+Date: Wed Jul 18 13:45:14 2012 -0700
+
+ intel: Quiet valgrind warnings in context creation.
+
+commit c10b08d95954aecd331e5a43b4861c6c04b8aadd
+Author: Damien Lespiau <damien.lesp...@intel.com>
+Date: Thu Jul 26 17:50:09 2012 +0100
+
+ intel: Remove two unused variables
+
+ Signed-off-by: Damien Lespiau <damien.lesp...@intel.com>
+ Reviewed-by: Eric Anholt <e...@anholt.net>
+
+commit ebd7904877d08525beb5039e4ea2f5b6c0a7c23f
+Author: Rob Clark <r...@ti.com>
+Date: Mon Jul 23 11:35:06 2012 -0500
+
+ modetest: fix uninitialized fourcc
+
+ If color format for CRTC layer is not specified on commandline, then
+ c->fourcc is unintialized resulting in addfb call failing.
+
+ Signed-off-by: Rob Clark <r...@ti.com>
+
+commit db004badef9315ba6a5f165d0974dd5afd5a6178
+Author: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+Date: Fri Jul 20 16:37:00 2012 +0200
+
+ modeset: Split buffer allocation to a separate file
+
+ As the modeset test application is often referred to as an example of
+ the KMS API usage, move test pattern generation and buffer allocation to
+ a separate file to keep it simple and clear.
+
+ Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+
+commit cc90ffa9b18fc6f925a3a2c36131332b8af558f8
+Author: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+Date: Fri Jul 20 14:50:48 2012 +0200
+
+ modetest: Make frame buffer format configurable on the command line
+
+ Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+
+commit 0375222c714e8b7ba55f12d5cb389383be1cf54d
+Author: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+Date: Fri Jul 20 14:50:47 2012 +0200
+
+ modetest: Move connector and plane parsing to separate functions
+
+ This will make it easier to add additional parameters to the connector
+ and plane arguments.
+
+ Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+
+commit edcef53685edf5fb94a1171f003b9516a90df368
+Author: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+Date: Fri Jul 20 14:50:46 2012 +0200
+
+ modetest: Add test pattern support for missing RGB formats
+
+ Implement tiles and SMPTE test pattern generation for the RGB565,
+ BGR888, RGB888, ARGB8888, BGRA8888 and BGRX8888 formats.
+
+ Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+
+commit 86402a2a0cf4f1c4dfa25d36043abd07a8cf8373
+Author: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+Date: Fri Jul 20 14:50:45 2012 +0200
+
+ modetest: Add test pattern support for missing planar YUV formats
+
+ Implement tiles and SMPTE test pattern generation for the NV12, NV21,
+ NV16 and NV61 formats.
+
+ Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+
+commit 8b6f3e32b8c6235e686525d766402c4fc6afcfba
+Author: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+Date: Fri Jul 20 14:50:44 2012 +0200
+
+ modetest: Add test pattern support for missing packed YUV formats
+
+ Implement tiles and SMPTE test pattern generation for the UYVY, VYUY and
+ YVYU formats.
+
+ Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+
+commit a94ee624292bff96ea1d38e8a0a3fbeefec42fb6
+Author: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+Date: Fri Jul 20 14:50:42 2012 +0200
+
+ modetest: Add SMPTE test pattern
+
+ Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+
+commit 3fdc1777ee156ebfa4281b49d8783adbbcae3ee1
+Author: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+Date: Fri Jul 20 14:50:41 2012 +0200
+
+ modetest: Unify buffer allocation
+
+ Merge the create_test_buffer() and create_grey_buffer() functions into a
+ single buffer allocation function that takes the pixel format and fill
+ pattern as parameters.
+
+ Signed-off-by: Laurent Pinchart <laurent.pinch...@ideasonboard.com>
+
+commit faf26b689d4a2a6d1e851a1ea2fd657406eebfff
+Author: Rob Clark <r...@ti.com>
+Date: Fri Jul 20 10:26:11 2012 -0500
+
+ intel: fix build error
+
+ CCLD test_decode
+ ./.libs/libdrm_intel.so: undefined reference to `drmPrimeHandleToFD'
+ ./.libs/libdrm_intel.so: undefined reference to `drmPrimeFDToHandle'
+ collect2: ld returned 1 exit status
+
+ From Adam Jackson's explaination:
+
+ most distros have changed it so ld defaults to
--no-copy-dt-needed-entries,
+ so if you use something from libdrm you can't just assume libdrm_intel
+ will bring it in for you, you have to be explicit
+
+ Signed-off-by: Rob Clark <r...@ti.com>
+
+commit ff65de96660965e661175f75427cd0020ef1104c
+Author: Dave Airlie <airl...@gmail.com>
+Date: Sun Jul 15 00:22:46 2012 +0000
+
+ intel: add prime interface for getting/setting a prime bo. (v4)
+
+ This adds interfaces for the X driver to use to create a
+ prime handle from a buffer, and create a bo from a handle.
+
+ v2: use Chris's suggested naming (well from at least for consistency)
+ v3: git commit --amend fail
+ v4: fix as per Chris's suggestions, group assignments, add get tiling
+
+ Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
+ Signed-off-by: Dave Airlie <airl...@redhat.com>
+
+commit 13c06cde4e9a4ce275c6cbf477d211344f468dbf
+Author: Dave Airlie <airl...@redhat.com>
+Date: Mon Jul 16 02:51:37 2012 +0100
+
+ libdrm/nouveau: add prime handle->bo and bo->handle support.
+
+ This adds prime support to nouveau libdrm.
+
+ Signed-off-by: Dave Airlie <airl...@redhat.com>
+
+commit cc0a14575d9fd0aafe73cb4aa445eaf024436114
+Author: Dave Airlie <airl...@gmail.com>
+Date: Sat Jul 14 09:52:17 2012 +0000
+
+ libdrm: add prime fd->handle and handle->fd interfaces
+
+ These are just basic ioctl wrappers around the prime ioctls,
+ along with the capability reporting.
+
+ Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
+ Signed-off-by: Dave Airlie <airl...@redhat.com>
+
+commit 41dfb20cdc369bb0da880c371a664f25fe665adb
+Author: Dave Airlie <airl...@gmail.com>
+Date: Sat Jul 14 09:52:16 2012 +0000
+
+ libdrm: add missing caps from kernel to drm.h
+
+ This just moves over some missing caps from the kernel.
+
+ Signed-off-by: Dave Airlie <airl...@redhat.com>
+ Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
+
+commit 22574aa887efa879519328acc09cb01d03374bf4
+Author: Rob Clark <r...@ti.com>
+Date: Fri Jul 13 16:18:25 2012 -0500
+
+ omap: add refcnting and handle tracking
+
+ There can be scenarios, especially when re-importing an existing buffer,
+ where you end up with multiple 'struct omap_bo's wrapping a single GEM
+ object handle. Which causes badness when the first of the evil-clones
+ is omap_bo_del()'d.
+
+ To do this, introduce reference counting and a hashtable to track the
+ handles per fd.
+
+ First, to avoid bo's slipping through the crack if multiple 'struct
+ omap_device's are created for one drm fd, a hashtable mapping drm
+ fd to omap_device, and the omap_device itself is reference counted.
+ Per omap_device, we keep a handle_table mapping GEM handle to omap_bo.
+ When buffers are imported from flink name or dmabuf fd, the handle
+ table is consulted, and if an omap_bo already exists, it's refcnt is
+ incremented and it is returned. For good measure, to avoid the
+ handle_table being deleted before the omap_bo is freed, the omap_bo
+ holds a reference to the omap_device.
+
+ TODO: check the overhead of the hashtable. If too much we could maybe
+ get away with only tracking exported and imported bo's in the table.
+
+ TODO: all the import/export flink/dmabuf operations are generic DRM
+ ioctls. Really all this functionality could be handled by a generic
+ drm_bo and drm_device "base class" that could be extended by omap,
+ exynos, etc. That would also allow more common userspace code by
+ avoiding artificial libdrm_omap dependencies.
+
+ Signed-off-by: Rob Clark <r...@ti.com>
+
+commit 42f8a68e19ba48a25f5eca2778d997f3d1ad094d
+Author: Rob Clark <r...@ti.com>
+Date: Mon Jun 11 17:17:17 2012 -0500
+
+ omap: add API to import bo's from dmabuf fd's
+
+ Signed-off-by: Rob Clark <r...@ti.com>
+
+commit 8116a32df613df4433aa1b128c58bf2c18479824
+Author: Rob Clark <r...@ti.com>
+Date: Mon Jun 11 08:52:24 2012 -0500
+
+ omap: clarify dmabuf file descriptor ownership
+
+ Signed-off-by: Rob Clark <r...@ti.com>
+
+commit 992e2afd59539d169689bf21d78fac8b5cea4e3c
+Author: Kenneth Graunke <kenn...@whitecape.org>
+Date: Thu Jul 12 13:41:11 2012 -0700
+
+ intel: Change context create failure message to from fprintf to DBG().
+
+ Since there is no getparam for hardware context support, Mesa always
+ tries to obtain a context by calling drm_intel_gem_context_create and
+ NULL-checking the result. On an older kernel without context support,
+ this caused libdrm to print an unwanted message to stderr:
+
+ DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: Invalid argument
+
+ In fact, this caused every Piglit test to fail with a "warn" status due
+ to the unrecognized error message.
+
+ Change the message to use DBG() rather than fprintf(), so people can
+ still get the debug message, but it won't spam normally.
+
+ Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
+ Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
+
+commit 881e69f185d2450ca35964caf254b04e7e8838c1
+Author: Cooper Yuan <coopery...@gmail.com>
+Date: Fri Jul 6 16:26:49 2012 +0200
+
+ libdrm/exynos: padding gem_mmap structure to 64-bit aligned
+
+commit 8fad46b614a156e3a0e65cd0af4c132a5820d29e
+Author: Lauri Kasanen <c...@gmx.com>
+Date: Sat Jun 30 13:12:45 2012 +0300
+
+ intel: Fix build failure in test_decode.c
+
+ Hi list
+
+ The recently released libdrm 2.4.37 does not compile the Intel part:
+
+ test_decode.c: In function 'compare_batch':
+ test_decode.c:107: error: implicit declaration of function 'open_memstream'
+
+ PS: Please CC me.
+
+ Signed-off-by: Lauri Kasanen <c...@gmx.com>
+ Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
+
commit 1b1a4f0a779f7ab2ba5673b9c9fe2a37047fe765
Author: Ben Widawsky <b...@bwidawsk.net>
Date: Fri Jun 29 11:08:05 2012 -0700
diff --git a/debian/changelog b/debian/changelog
index f8b5432..b0ef02f 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-libdrm (2.4.37-1) UNRELEASED; urgency=low
+libdrm (2.4.38-1) UNRELEASED; urgency=low
[ Maarten Lankhorst ]
* New upstream release.
commit d1de6831b9f49b1f450324948b6a4759b3f7ae04
Author: Marek Olšák <mar...@gmail.com>
Date: Sat Aug 11 20:05:24 2012 +0200
configure: bump version for 2.4.38 release
diff --git a/configure.ac b/configure.ac
index 3eaec74..3e2792e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.37],
+ [2.4.38],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit 10481fec55b422843d3f15eef3aa9617ae98843b
Author: Marek Olšák <mar...@gmail.com>
Date: Sat Aug 11 20:02:03 2012 +0200
tests/modetest: fix distcheck
diff --git a/tests/modetest/Makefile.am b/tests/modetest/Makefile.am
index 35754a2..b5ec771 100644
--- a/tests/modetest/Makefile.am
+++ b/tests/modetest/Makefile.am
@@ -8,7 +8,8 @@ noinst_PROGRAMS = \
modetest
modetest_SOURCES = \
- buffers.c modetest.c
+ buffers.c modetest.c buffers.h
+
modetest_LDADD = \
$(top_builddir)/libdrm.la \
$(top_builddir)/libkms/libkms.la \
commit 2607dad20b8dffce96608103def75d26ea0e42b2
Author: Eric Anholt <e...@anholt.net>
Date: Wed Aug 1 16:43:16 2012 -0700
intel: Add a function for the new register read ioctl.
Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h
index 2167e43..8d7f239 100644
--- a/intel/intel_bufmgr.h
+++ b/intel/intel_bufmgr.h
@@ -241,6 +241,9 @@ void drm_intel_decode_set_head_tail(struct drm_intel_decode
*ctx,
void drm_intel_decode_set_output_file(struct drm_intel_decode *ctx, FILE *out);
void drm_intel_decode(struct drm_intel_decode *ctx);
+int drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
+ uint32_t offset,
+ uint64_t *result);
/** @{ Compatibility defines to keep old code building despite the symbol
rename
* from dri_* to drm_intel_*
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index ec64e0a..0ea6260 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2947,6 +2947,24 @@ drm_intel_gem_context_destroy(drm_intel_context *ctx)
free(ctx);
}
+int
+drm_intel_reg_read(drm_intel_bufmgr *bufmgr,
+ uint32_t offset,
+ uint64_t *result)
+{
+ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
+ struct drm_i915_reg_read reg_read;
+ int ret;
+
+ VG_CLEAR(reg_read);
+ reg_read.offset = offset;
+
+ ret = drmIoctl(bufmgr_gem->fd, DRM_IOCTL_I915_REG_READ, ®_read);
+
+ *result = reg_read.val;
+ return ret;
+}
+
/**
* Annotate the given bo for use in aub dumping.
commit 934ea3b32127ea2a4ba5bf14228af6c60d3437b6
Author: Eric Anholt <e...@anholt.net>
Date: Wed Aug 1 16:38:19 2012 -0700
intel: Import updated i915_drm.h.
Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 5c8fabe..7e9e9bd 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -195,6 +195,9 @@ typedef struct _drm_i915_sarea {
#define DRM_I915_GEM_WAIT 0x2c
#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
+#define DRM_I915_GEM_SET_CACHEING 0x2f
+#define DRM_I915_GEM_GET_CACHEING 0x30
+#define DRM_I915_REG_READ 0x31
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE +
DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE +
DRM_I915_FLUSH)
@@ -219,6 +222,8 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE +
DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
+#define DRM_IOCTL_I915_GEM_SET_CACHEING
DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHEING, struct
drm_i915_gem_cacheing)
+#define DRM_IOCTL_I915_GEM_GET_CACHEING
DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHEING, struct
drm_i915_gem_cacheing)
#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE +
DRM_I915_GEM_THROTTLE)
#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE +
DRM_I915_GEM_LEAVEVT)
@@ -241,6 +246,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE +
DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE +
DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
+#define DRM_IOCTL_I915_REG_READ DRM_IOWR
(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
/* Allow drivers to submit batchbuffers directly to hardware, relying
* on the security mechanisms provided by hardware.
@@ -690,10 +696,31 @@ struct drm_i915_gem_busy {
/** Handle of the buffer to check for busy */
__u32 handle;
- /** Return busy status (1 if busy, 0 if idle) */
+ /** Return busy status (1 if busy, 0 if idle).
+ * The high word is used to indicate on which rings the object
+ * currently resides:
+ * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
+ */
__u32 busy;
};
+#define I915_CACHEING_NONE 0
+#define I915_CACHEING_CACHED 1
+
+struct drm_i915_gem_cacheing {
+ /**
+ * Handle of the buffer to set/get the cacheing level of. */
+ __u32 handle;
+
+ /**
+ * Cacheing level to apply or return value
+ *
+ * bits0-15 are for generic cacheing control (i.e. the above defined
+ * values). bits16-31 are reserved for platform-specific variations
+ * (e.g. l3$ caching on gen7). */
+ __u32 cacheing;
+};
+
#define I915_TILING_NONE 0
#define I915_TILING_X 1
#define I915_TILING_Y 2
@@ -910,4 +937,8 @@ struct drm_i915_gem_context_destroy {
__u32 pad;
};
+struct drm_i915_reg_read {
+ __u64 offset;
+ __u64 val; /* Return value */
+};
#endif /* _I915_DRM_H_ */
commit 71ebcf4ea372927ba8af425a229c4fa75dc45dd1
Author: Eric Anholt <e...@anholt.net>
Date: Thu Aug 2 11:25:57 2012 -0700
Drop "-Wunsafe-loop-optimizations".
It warns about totally sensible things done in intel_decode.c. I've
never seen this warn do anything useful, and apparently I was the one
to introduce it when I added the giant pile of warning flags back in
2008.
Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
diff --git a/configure.ac b/configure.ac
index 09fed53..3eaec74 100644
--- a/configure.ac
+++ b/configure.ac
@@ -133,7 +133,7 @@ MAYBE_WARN="-Wall -Wextra \
-Wpointer-arith -Wwrite-strings -Wstrict-prototypes \
-Wmissing-prototypes -Wmissing-declarations -Wnested-externs \
-Wpacked -Wswitch-enum -Wmissing-format-attribute \
--Wstrict-aliasing=2 -Winit-self -Wunsafe-loop-optimizations \
+-Wstrict-aliasing=2 -Winit-self \
-Wdeclaration-after-statement -Wold-style-definition \
-Wno-missing-field-initializers -Wno-unused-parameter \
-Wno-attributes -Wno-long-long -Winline"
commit 128803a107fde8ce36036e59437a536fc4d46553
Author: Marek Olšák <mar...@gmail.com>
Date: Tue Aug 7 23:38:19 2012 +0200
radeon: tweak TILE_SPLIT for MSAA surfaces
Reviewed-by: Jerome Glisse <jgli...@redhat.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 499e994..892dca6 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -871,12 +871,37 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
return 0;
}
- /* set tile split to row size, optimize latter for multi-sample surface
- * tile split >= 256 for render buffer surface. Also depth surface want
- * smaller value for optimal performances.
- */
- surf->tile_split = surf_man->hw_info.row_size;
- surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
+ /* Tweak TILE_SPLIT for performance here. */
+ if (surf->nsamples > 1) {
+ if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
+ switch (surf->nsamples) {
+ case 2:
+ surf->tile_split = 128;
+ break;
+ case 4:
+ surf->tile_split = 128;
+ break;
+ case 8:
+ surf->tile_split = 256;
+ break;
+ case 16: /* cayman only */
+ surf->tile_split = 512;
+ break;
+ default:
+ fprintf(stderr, "radeon: Wrong number of samples %i (%i)\n",
+ surf->nsamples, __LINE__);
+ return -EINVAL;
+ }
+ surf->stencil_tile_split = 64;
+ } else {
+ /* tile split must be >= 256 for colorbuffer surfaces */
+ surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
+ }
+ } else {
+ /* set tile split to row size */
+ surf->tile_split = surf_man->hw_info.row_size;
+ surf->stencil_tile_split = surf_man->hw_info.row_size / 2;
+ }
/* bankw or bankh greater than 1 increase alignment requirement, not
* sure if it's worth using smaller bankw & bankh to stick with 2D
commit e14aedce64e365ef1a8726ed8c1ebed881d7a398
Author: Marek Olšák <mar...@gmail.com>
Date: Tue Aug 7 22:50:39 2012 +0200
radeon: force 2D tiling for MSAA surfaces
Reviewed-by: Jerome Glisse <jgli...@redhat.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 874a092..499e994 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -154,7 +154,7 @@ static void surf_minify(struct radeon_surface *surf,
surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1)
/ surf->blk_w;
surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1)
/ surf->blk_h;
surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1)
/ surf->blk_d;
- if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D)
{
if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y <
yalign) {
surf->level[level].mode = RADEON_SURF_MODE_1D;
return;
@@ -382,6 +382,12 @@ static int r6_surface_init(struct radeon_surface_manager
*surf_man,
unsigned mode;
int r;
+ /* MSAA surfaces support the 2D mode only. */
+ if (surf->nsamples > 1) {
+ surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
+ surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ }
+
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
@@ -401,6 +407,10 @@ static int r6_surface_init(struct radeon_surface_manager
*surf_man,
/* force 1d on kernel that can't do 2d */
if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
+ if (surf->nsamples > 1) {
+ fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface
(%i).\n", __LINE__);
+ return -EFAULT;
+ }
mode = RADEON_SURF_MODE_1D;
surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
surf->flags |= RADEON_SURF_SET(mode, MODE);
@@ -548,7 +558,7 @@ static void eg_surf_minify(struct radeon_surface *surf,
surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1)
/ surf->blk_w;
surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1)
/ surf->blk_h;
surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1)
/ surf->blk_d;
- if (surf->level[level].mode == RADEON_SURF_MODE_2D) {
+ if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D)
{
if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y <
mtileh) {
surf->level[level].mode = RADEON_SURF_MODE_1D;
return;
@@ -687,6 +697,10 @@ static int eg_surface_sanity(struct radeon_surface_manager
*surf_man,
/* force 1d on kernel that can't do 2d */
if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) {
+ if (surf->nsamples > 1) {
+ fprintf(stderr, "radeon: Cannot use 2D tiling for an MSAA surface
(%i).\n", __LINE__);
+ return -EFAULT;
+ }
mode = RADEON_SURF_MODE_1D;
surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
surf->flags |= RADEON_SURF_SET(mode, MODE);
@@ -754,6 +768,12 @@ static int eg_surface_init(struct radeon_surface_manager
*surf_man,
unsigned mode;
int r;
+ /* MSAA surfaces support the 2D mode only. */
+ if (surf->nsamples > 1) {
+ surf->flags = RADEON_SURF_CLR(surf->flags, MODE);
+ surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
+ }
+
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
commit 23372955730048bbcddafc74365d911f9a74fb13
Author: Marek Olšák <mar...@gmail.com>
Date: Sun Jul 29 15:20:15 2012 +0200
radeon: optimize allocation for depth w/o stencil and stencil w/o depth on
EG
If we don't need stencil, don't allocate it.
If we need only stencil (like PIPE_FORMAT_S8_UINT), don't allocate depth.
v2: actually do it correctly
Reviewed-by: Christian König <christian.koe...@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 5800c33..874a092 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -604,7 +604,11 @@ static int eg_surface_init_1d(struct
radeon_surface_manager *surf_man,
}
}
- if (surf->flags & RADEON_SURF_SBUFFER) {
+ /* The depth and stencil buffers are in separate resources on evergreen.
+ * We allocate them in one buffer next to each other to simplify
+ * communication between the DDX and the Mesa driver. */
+ if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
+ (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
}
@@ -656,7 +660,8 @@ static int eg_surface_init_2d(struct radeon_surface_manager
*surf_man,
}
}
- if (surf->flags & RADEON_SURF_SBUFFER) {
+ if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
+ (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
}
@@ -752,14 +757,7 @@ static int eg_surface_init(struct radeon_surface_manager
*surf_man,
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
- /* for some reason eg need to have room for stencil right after depth */
- if (surf->flags & RADEON_SURF_ZBUFFER) {
- surf->flags |= RADEON_SURF_SBUFFER;
- }
- if (surf->flags & RADEON_SURF_SBUFFER) {
- surf->flags |= RADEON_SURF_ZBUFFER;
- }
- if (surf->flags & RADEON_SURF_ZBUFFER) {
+ if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
/* zbuffer only support 1D or 2D tiled surface */
switch (mode) {
case RADEON_SURF_MODE_1D:
@@ -828,11 +826,6 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
- /* for some reason eg need to have room for stencil right after depth */
- if (surf->flags & RADEON_SURF_ZBUFFER) {
- surf->flags |= RADEON_SURF_SBUFFER;
- }
-
/* set some default value to avoid sanity check choking on them */
surf->tile_split = 1024;
surf->bankw = 1;
commit ad66c17209811acdae21e44290a449523882a734
Author: Marek Olšák <mar...@gmail.com>
Date: Sun Jul 29 14:10:07 2012 +0200
radeon: simplify ZS buffer checking on r600
Setting those flags has no effect anywhere else.
Reviewed-by: Christian König <christian.koe...@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index c80f7f4..5800c33 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -385,14 +385,7 @@ static int r6_surface_init(struct radeon_surface_manager
*surf_man,
/* tiling mode */
mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK;
- /* always enable z & stencil together */
- if (surf->flags & RADEON_SURF_ZBUFFER) {
- surf->flags |= RADEON_SURF_SBUFFER;
- }
- if (surf->flags & RADEON_SURF_SBUFFER) {
- surf->flags |= RADEON_SURF_ZBUFFER;
- }
- if (surf->flags & RADEON_SURF_ZBUFFER) {
+ if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
/* zbuffer only support 1D or 2D tiled surface */
switch (mode) {
case RADEON_SURF_MODE_1D:
commit 93fef04b1e3a83e2f884880ed1c3395f67b038ab
Author: Paulo Zanoni <paulo.r.zan...@intel.com>
Date: Mon Aug 6 14:55:23 2012 -0300
intel: add more Haswell PCI IDs
Signed-off-by: Paulo Zanoni <paulo.r.zan...@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.v...@gmail.com>
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 9c1abc8..b73fa0f 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -48,9 +48,40 @@
#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
#define PCI_CHIP_HASWELL_GT2 0x0412
+#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_ULT_GT2 0x0A16 /* Mobile ULT */
+#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
+#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
+#define PCI_CHIP_HASWELL_S_GT2 0x041A
+#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
+#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
+#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
+#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
+#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
+#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
+#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
+#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
--
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