.gitignore | 4
Makefile.am | 2
configure.ac | 50 +++++-
intel/intel_bufmgr_gem.c | 10 +
intel/intel_chipset.h | 7
intel/intel_decode.c | 2
libkms/Makefile.am | 2
man/Makefile.am | 11 +
man/drmAvailable.man | 25 +++
man/drmHandleEvent.man | 45 +++++
man/drmModeGetResources.man | 79 ++++++++++
omap/omap_drm.c | 2
radeon/r600_pci_ids.h | 3
radeon/radeon_cs_gem.c | 2
radeon/radeon_surface.c | 333 +++++++++++++++++++++++++++++++++-----------
radeon/radeon_surface.h | 2
tests/modetest/Makefile.am | 11 -
xf86drmMode.c | 5
18 files changed, 499 insertions(+), 96 deletions(-)
New commits:
commit e01d68f9f3acfc35fe164283904b5d058c2ab378
Author: Marek Olšák <mar...@gmail.com>
Date: Tue Nov 6 01:23:53 2012 +0100
configure.ac: bump version to 2.4.40 for release
diff --git a/configure.ac b/configure.ac
index 8c28107..0c19929 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.39],
+ [2.4.40],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit 2089a0080edb1b42449ee9a97f2cef7399c16d53
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Nov 5 22:21:42 2012 +0000
fix make distcheck
typo,
Reported-by: mareko on irc
Signed-off-by: Dave Airlie <airl...@redhat.com>
diff --git a/man/Makefile.am b/man/Makefile.am
index 73068e6..ccd6545 100644
--- a/man/Makefile.am
+++ b/man/Makefile.am
@@ -4,7 +4,7 @@ libman_PRE = drmAvailable.man \
drmModeGetResources.man
libman_DATA = $(libman_PRE:man=@LIB_MAN_SUFFIX@)
EXTRA_DIST = $(libman_PRE)
-CLEANFILE = $(libman_DATA)
+CLEANFILES = $(libman_DATA)
SUFFIXES = .$(LIB_MAN_SUFFIX) .man
.man.$(LIB_MAN_SUFFIX):
commit e32fff8e9ea8d522679eaab21a9555cab134fb36
Author: Marek Olšák <mar...@gmail.com>
Date: Tue Oct 16 02:08:02 2012 +0200
radeon: fix tile_split of 128-bit surface formats with 8x MSAA
The calculation led to the number 8192, which is too high.
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 66c2444..eb587d2 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -939,6 +939,8 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
} else {
/* tile split must be >= 256 for colorbuffer surfaces */
surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256);
+ if (surf->tile_split > 4096)
+ surf->tile_split = 4096;
}
} else {
/* set tile split to row size */
commit bc494b310d76f701798aee0f2b0b472d608cbfaf
Author: Andreas Boll <andreas.boll....@gmail.com>
Date: Tue Aug 28 12:49:45 2012 +0200
radeon: fix unused-function warning
radeon_cs_gem.c:333:13: warning: 'cs_gem_dump_bof' defined but
not used [-Wunused-function]
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c
index 9834bcf..b963140 100644
--- a/radeon/radeon_cs_gem.c
+++ b/radeon/radeon_cs_gem.c
@@ -330,6 +330,7 @@ static int cs_gem_end(struct radeon_cs_int *cs,
return 0;
}
+#if CS_BOF_DUMP
static void cs_gem_dump_bof(struct radeon_cs_int *cs)
{
struct cs_gem *csg = (struct cs_gem*)cs;
@@ -415,6 +416,7 @@ out_err:
bof_decref(device_id);
bof_decref(root);
}
+#endif
static int cs_gem_emit(struct radeon_cs_int *cs)
{
commit a4cb7233a8da171e53b48b376be5c1265c29a612
Author: Alex Deucher <alexander.deuc...@amd.com>
Date: Tue Oct 16 12:58:39 2012 -0400
radeon: add some new SI pci ids
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h
index 12daafd..b9a85db 100644
--- a/radeon/r600_pci_ids.h
+++ b/radeon/r600_pci_ids.h
@@ -318,6 +318,8 @@ CHIPSET(0x6784, TAHITI_6784, TAHITI)
CHIPSET(0x6788, TAHITI_6788, TAHITI)
CHIPSET(0x678A, TAHITI_678A, TAHITI)
CHIPSET(0x6790, TAHITI_6790, TAHITI)
+CHIPSET(0x6791, TAHITI_6791, TAHITI)
+CHIPSET(0x6792, TAHITI_6792, TAHITI)
CHIPSET(0x6798, TAHITI_6798, TAHITI)
CHIPSET(0x6799, TAHITI_6799, TAHITI)
CHIPSET(0x679A, TAHITI_679A, TAHITI)
@@ -331,6 +333,7 @@ CHIPSET(0x6806, PITCAIRN_6806, PITCAIRN)
CHIPSET(0x6808, PITCAIRN_6808, PITCAIRN)
CHIPSET(0x6809, PITCAIRN_6809, PITCAIRN)
CHIPSET(0x6810, PITCAIRN_6810, PITCAIRN)
+CHIPSET(0x6811, PITCAIRN_6811, PITCAIRN)
CHIPSET(0x6816, PITCAIRN_6816, PITCAIRN)
CHIPSET(0x6817, PITCAIRN_6817, PITCAIRN)
CHIPSET(0x6818, PITCAIRN_6818, PITCAIRN)
commit e81acf51013d5d4245417c46ee6b4055c26f1a91
Author: Rob Clark <r...@ti.com>
Date: Sun Oct 14 16:55:32 2012 -0500
initialize width/height fields in drmModeCrtc
If we have valid timings, we can at least set width/height to
*something*, which is I think at least less confusing than always
seeing width/height of zero. At least modeprint and modetest
seem to expect width/height to mean something.
Signed-off-by: Rob Clark <r...@ti.com>
diff --git a/xf86drmMode.c b/xf86drmMode.c
index 04fdf1f..f603ceb 100644
--- a/xf86drmMode.c
+++ b/xf86drmMode.c
@@ -351,8 +351,11 @@ drmModeCrtcPtr drmModeGetCrtc(int fd, uint32_t crtcId)
r->x = crtc.x;
r->y = crtc.y;
r->mode_valid = crtc.mode_valid;
- if (r->mode_valid)
+ if (r->mode_valid) {
memcpy(&r->mode, &crtc.mode, sizeof(struct drm_mode_modeinfo));
+ r->width = crtc.mode.hdisplay;
+ r->height = crtc.mode.vdisplay;
+ }
r->buffer_id = crtc.fb_id;
r->gamma_size = crtc.gamma_size;
return r;
commit 844d75e5a0b3b8f3466a24256955e886275fb298
Author: Rob Clark <r...@ti.com>
Date: Tue Oct 9 09:48:56 2012 -0500
update gitignore
Signed-off-by: Rob Clark <r...@ti.com>
diff --git a/.gitignore b/.gitignore
index 243457e..28c77c5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -42,6 +42,8 @@ libdrm.pc
libdrm_intel.pc
libdrm_nouveau.pc
libdrm_radeon.pc
+libdrm_omap.pc
+libdrm_exynos.pc
libkms.pc
libtool
ltmain.sh
@@ -76,3 +78,5 @@ tests/modeprint/modeprint
tests/modetest/modetest
tests/kmstest/kmstest
tests/vbltest/vbltest
+tests/radeon/radeon_ttm
+man/*.3
commit 28a13f0be734958c74ae5a23d9cf766fa0857a62
Author: Vincent Penquerc'h <vincent.penque...@collabora.co.uk>
Date: Tue Oct 9 14:48:34 2012 +0100
omap: release lock also on error paths
Signed-off-by: Rob Clark <r...@ti.com>
diff --git a/omap/omap_drm.c b/omap/omap_drm.c
index cd8e8bc..89f1491 100644
--- a/omap/omap_drm.c
+++ b/omap/omap_drm.c
@@ -304,6 +304,7 @@ struct omap_bo * omap_bo_from_name(struct omap_device *dev,
uint32_t name)
return bo;
fail:
+ pthread_mutex_unlock(&table_lock);
free(bo);
return NULL;
}
@@ -337,6 +338,7 @@ struct omap_bo * omap_bo_from_dmabuf(struct omap_device
*dev, int fd)
return bo;
fail:
+ pthread_mutex_unlock(&table_lock);
free(bo);
return NULL;
}
commit 14db948127e549ea9234e02d8e112de3871f8f9f
Author: Daniel Stone <dan...@fooishbar.org>
Date: Thu Oct 4 01:21:57 2012 +0000
configure.ac: Allow forcible disabling of Cairo support
We don't want to build libdrm tests with Cairo support under Poky, since
they're never used and also cause a build loop from libdrm -> cairo ->
mesa-dri -> libdrm.
To avoid variance in build results, introduce a --disable-cairo-tests
switch.
Signed-off-by: Daniel Stone <dan...@fooishbar.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
diff --git a/configure.ac b/configure.ac
index 290362c..8c28107 100644
--- a/configure.ac
+++ b/configure.ac
@@ -222,11 +222,23 @@ if test "x$EXYNOS" = xyes; then
AC_DEFINE(HAVE_EXYNOS, 1, [Have EXYNOS support])
fi
+AC_ARG_ENABLE([cairo-tests],
+ [AS_HELP_STRING([--enable-cairo-tests],
+ [Enable support for Cairo rendering in tests
(default: auto)])],
+ [CAIRO=$enableval], [CAIRO=auto])
PKG_CHECK_MODULES(CAIRO, cairo, [HAVE_CAIRO=yes], [HAVE_CAIRO=no])
-if test "x$HAVE_CAIRO" = xyes; then
- AC_DEFINE(HAVE_CAIRO, 1, [Have cairo support])
+AC_MSG_CHECKING([whether to enable Cairo tests])
+if test "x$CAIRO" = xauto; then
+ CAIRO="$HAVE_CAIRO"
fi
-AM_CONDITIONAL(HAVE_CAIRO, [test "x$HAVE_CAIRO" = xyes])
+if test "x$CAIRO" = xyes; then
+ if ! test "x$HAVE_CAIRO" = xyes; then
+ AC_MSG_ERROR([Cairo support required but not present])
+ fi
+ AC_DEFINE(HAVE_CAIRO, 1, [Have Cairo support])
+fi
+AC_MSG_RESULT([$CAIRO])
+AM_CONDITIONAL(HAVE_CAIRO, [test "x$CAIRO" = xyes])
# For enumerating devices in test case
PKG_CHECK_MODULES(LIBUDEV, libudev, [HAVE_LIBUDEV=yes], [HAVE_LIBUDEV=no])
diff --git a/tests/modetest/Makefile.am b/tests/modetest/Makefile.am
index b5ec771..065ae13 100644
--- a/tests/modetest/Makefile.am
+++ b/tests/modetest/Makefile.am
@@ -1,8 +1,7 @@
AM_CFLAGS = \
-I$(top_srcdir)/include/drm \
-I$(top_srcdir)/libkms/ \
- -I$(top_srcdir) \
- $(CAIRO_CFLAGS)
+ -I$(top_srcdir)
noinst_PROGRAMS = \
modetest
@@ -12,5 +11,9 @@ modetest_SOURCES = \
modetest_LDADD = \
$(top_builddir)/libdrm.la \
- $(top_builddir)/libkms/libkms.la \
- $(CAIRO_LIBS)
+ $(top_builddir)/libkms/libkms.la
+
+if HAVE_CAIRO
+AM_CFLAGS += $(CAIRO_CFLAGS)
+modetest_LDADD += $(CAIRO_LIBS)
+endif
commit a83444c925b18b3db431336360d6915aaf21f727
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Sun Oct 7 10:08:46 2012 +0100
intel: Silence a trivial compiler warning
intel_bufmgr_gem.c: In function 'drm_intel_bo_gem_export_to_prime':
intel_bufmgr_gem.c:2477:6: warning: unused variable 'ret'
[-Wunused-variable]
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 3f7424c..8d45839 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -2472,7 +2472,6 @@ drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int
*prime_fd)
{
drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr;
drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo;
- int ret;
if (drmPrimeHandleToFD(bufmgr_gem->fd, bo_gem->gem_handle,
DRM_CLOEXEC, prime_fd) != 0)
commit 8cf3475eb5d887c361db372a644d0d1a11e137f8
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Sun Oct 7 10:07:23 2012 +0100
intel: Correct the word decoding for gen2 3DSTATE_LOAD_STATE_IMMEDIATE_1
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 19a8d36..a4b045a 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -1714,7 +1714,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
}
} else {
instr_out(ctx, i,
- "S%d: 0x%08x\n", i, data[i]);
+ "S%d: 0x%08x\n", word,
data[i]);
}
i++;
}
commit 75830a0d2cbb614ecc3f7e6b516ec595bb41d6a3
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Sun Oct 7 10:05:19 2012 +0100
intel: Fix "properly test for HAS_LLC"
commit 92fd0ce4f659d7b0680543e9e5b96a3c7737a5f3
Author: Daniel Vetter <daniel.vet...@ffwll.ch>
Date: Fri Aug 31 11:16:53 2012 +0200
intel: properly test for HAS_LLC
missed slightly and in effect had no effect on the outcome of checking
whether the kernel/chipset supported LLC.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 898008d..3f7424c 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3119,7 +3119,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->has_llc = (IS_GEN6(bufmgr_gem->pci_device) |
IS_GEN7(bufmgr_gem->pci_device));
} else
- bufmgr_gem->has_llc = gp.value;
+ bufmgr_gem->has_llc = *gp.value;
if (bufmgr_gem->gen < 4) {
gp.param = I915_PARAM_NUM_FENCES_AVAIL;
commit 1aebfdc1121ccb6babb3a63dc0b99d68b4860b04
Author: Marek Olšák <mar...@gmail.com>
Date: Sun Sep 30 19:20:04 2012 +0200
radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI
This allows texturing with depth-stencil buffers directly without the copy
to CB. The separate miptree description for stencil is added, because
the stencil mipmap offsets are not really depth offsets/4 (at least
for the texture units).
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index c62cbf9..66c2444 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -144,31 +144,32 @@ static unsigned mip_minify(unsigned size, unsigned level)
}
static void surf_minify(struct radeon_surface *surf,
- unsigned level,
+ struct radeon_surface_level *surflevel,
+ unsigned bpe, unsigned level,
uint32_t xalign, uint32_t yalign, uint32_t zalign,
unsigned offset)
{
- surf->level[level].npix_x = mip_minify(surf->npix_x, level);
- surf->level[level].npix_y = mip_minify(surf->npix_y, level);
- surf->level[level].npix_z = mip_minify(surf->npix_z, level);
- surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1)
/ surf->blk_w;
- surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1)
/ surf->blk_h;
- surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1)
/ surf->blk_d;
- if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D)
{
- if (surf->level[level].nblk_x < xalign || surf->level[level].nblk_y <
yalign) {
- surf->level[level].mode = RADEON_SURF_MODE_1D;
+ surflevel->npix_x = mip_minify(surf->npix_x, level);
+ surflevel->npix_y = mip_minify(surf->npix_y, level);
+ surflevel->npix_z = mip_minify(surf->npix_z, level);
+ surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
+ surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
+ surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) {
+ surflevel->mode = RADEON_SURF_MODE_1D;
return;
}
}
- surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, xalign);
- surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, yalign);
- surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, zalign);
+ surflevel->nblk_x = ALIGN(surflevel->nblk_x, xalign);
+ surflevel->nblk_y = ALIGN(surflevel->nblk_y, yalign);
+ surflevel->nblk_z = ALIGN(surflevel->nblk_z, zalign);
- surf->level[level].offset = offset;
- surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe *
surf->nsamples;
- surf->level[level].slice_size = surf->level[level].pitch_bytes *
surf->level[level].nblk_y;
+ surflevel->offset = offset;
+ surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
+ surflevel->slice_size = surflevel->pitch_bytes * surflevel->nblk_y;
- surf->bo_size = offset + surf->level[level].slice_size *
surf->level[level].nblk_z * surf->array_size;
+ surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z *
surf->array_size;
}
/* ===========================================================================
@@ -264,7 +265,7 @@ static int r6_surface_init_linear(struct
radeon_surface_manager *surf_man,
/* build mipmap tree */
for (i = start_level; i <= surf->last_level; i++) {
surf->level[i].mode = RADEON_SURF_MODE_LINEAR;
- surf_minify(surf, i, xalign, yalign, zalign, offset);
+ surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign,
offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
if ((i == 0)) {
@@ -292,7 +293,7 @@ static int r6_surface_init_linear_aligned(struct
radeon_surface_manager *surf_ma
/* build mipmap tree */
for (i = start_level; i <= surf->last_level; i++) {
surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
- surf_minify(surf, i, xalign, yalign, zalign, offset);
+ surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign,
offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
if ((i == 0)) {
@@ -325,7 +326,7 @@ static int r6_surface_init_1d(struct radeon_surface_manager
*surf_man,
/* build mipmap tree */
for (i = start_level; i <= surf->last_level; i++) {
surf->level[i].mode = RADEON_SURF_MODE_1D;
- surf_minify(surf, i, xalign, yalign, zalign, offset);
+ surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign,
offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
if ((i == 0)) {
@@ -363,7 +364,7 @@ static int r6_surface_init_2d(struct radeon_surface_manager
*surf_man,
/* build mipmap tree */
for (i = start_level; i <= surf->last_level; i++) {
surf->level[i].mode = RADEON_SURF_MODE_2D;
- surf_minify(surf, i, xalign, yalign, zalign, offset);
+ surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign,
offset);
if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
return r6_surface_init_1d(surf_man, surf, offset, i);
}
@@ -543,6 +544,8 @@ static int eg_init_hw_info(struct radeon_surface_manager
*surf_man)
}
static void eg_surf_minify(struct radeon_surface *surf,
+ struct radeon_surface_level *surflevel,
+ unsigned bpe,
unsigned level,
unsigned slice_pt,
unsigned mtilew,
@@ -552,36 +555,38 @@ static void eg_surf_minify(struct radeon_surface *surf,
{
unsigned mtile_pr, mtile_ps;
- surf->level[level].npix_x = mip_minify(surf->npix_x, level);
- surf->level[level].npix_y = mip_minify(surf->npix_y, level);
- surf->level[level].npix_z = mip_minify(surf->npix_z, level);
- surf->level[level].nblk_x = (surf->level[level].npix_x + surf->blk_w - 1)
/ surf->blk_w;
- surf->level[level].nblk_y = (surf->level[level].npix_y + surf->blk_h - 1)
/ surf->blk_h;
- surf->level[level].nblk_z = (surf->level[level].npix_z + surf->blk_d - 1)
/ surf->blk_d;
- if (surf->nsamples == 1 && surf->level[level].mode == RADEON_SURF_MODE_2D)
{
- if (surf->level[level].nblk_x < mtilew || surf->level[level].nblk_y <
mtileh) {
- surf->level[level].mode = RADEON_SURF_MODE_1D;
+ surflevel->npix_x = mip_minify(surf->npix_x, level);
+ surflevel->npix_y = mip_minify(surf->npix_y, level);
+ surflevel->npix_z = mip_minify(surf->npix_z, level);
+ surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w;
+ surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h;
+ surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d;
+ if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D) {
+ if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) {
+ surflevel->mode = RADEON_SURF_MODE_1D;
return;
}
}
- surf->level[level].nblk_x = ALIGN(surf->level[level].nblk_x, mtilew);
- surf->level[level].nblk_y = ALIGN(surf->level[level].nblk_y, mtileh);
- surf->level[level].nblk_z = ALIGN(surf->level[level].nblk_z, 1);
+ surflevel->nblk_x = ALIGN(surflevel->nblk_x, mtilew);
+ surflevel->nblk_y = ALIGN(surflevel->nblk_y, mtileh);
+ surflevel->nblk_z = ALIGN(surflevel->nblk_z, 1);
/* macro tile per row */
- mtile_pr = surf->level[level].nblk_x / mtilew;
+ mtile_pr = surflevel->nblk_x / mtilew;
/* macro tile per slice */
- mtile_ps = (mtile_pr * surf->level[level].nblk_y) / mtileh;
+ mtile_ps = (mtile_pr * surflevel->nblk_y) / mtileh;
- surf->level[level].offset = offset;
- surf->level[level].pitch_bytes = surf->level[level].nblk_x * surf->bpe *
slice_pt;
- surf->level[level].slice_size = mtile_ps * mtileb * slice_pt;
+ surflevel->offset = offset;
+ surflevel->pitch_bytes = surflevel->nblk_x * bpe * slice_pt;
+ surflevel->slice_size = mtile_ps * mtileb * slice_pt;
- surf->bo_size = offset + surf->level[level].slice_size *
surf->level[level].nblk_z * surf->array_size;
+ surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z *
surf->array_size;
}
static int eg_surface_init_1d(struct radeon_surface_manager *surf_man,
struct radeon_surface *surf,
+ struct radeon_surface_level *level,
+ unsigned bpe,
uint64_t offset, unsigned start_level)
{
uint32_t xalign, yalign, zalign, tilew;
@@ -589,45 +594,40 @@ static int eg_surface_init_1d(struct
radeon_surface_manager *surf_man,
/* compute alignment */
tilew = 8;
- xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe *
surf->nsamples);
- if (surf->flags & RADEON_SURF_SBUFFER) {
- xalign = surf_man->hw_info.group_bytes / (tilew * surf->nsamples);
- }
+ xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples);
xalign = MAX2(tilew, xalign);
yalign = tilew;
zalign = 1;
if (surf->flags & RADEON_SURF_SCANOUT) {
- xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign);
+ xalign = MAX2((bpe == 1) ? 64 : 32, xalign);
}
+
if (!start_level) {
- surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes);
+ unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes);
+ surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
+
+ if (offset) {
+ offset = ALIGN(offset, alignment);
+ }
}
/* build mipmap tree */
for (i = start_level; i <= surf->last_level; i++) {
- surf->level[i].mode = RADEON_SURF_MODE_1D;
- surf_minify(surf, i, xalign, yalign, zalign, offset);
+ level[i].mode = RADEON_SURF_MODE_1D;
+ surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset);
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
if ((i == 0)) {
offset = ALIGN(offset, surf->bo_alignment);
}
}
-
- /* The depth and stencil buffers are in separate resources on evergreen.
- * We allocate them in one buffer next to each other to simplify
- * communication between the DDX and the Mesa driver. */
- if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
- (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
- surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
- surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
- }
-
return 0;
}
static int eg_surface_init_2d(struct radeon_surface_manager *surf_man,
struct radeon_surface *surf,
+ struct radeon_surface_level *level,
+ unsigned bpe, unsigned tile_split,
uint64_t offset, unsigned start_level)
{
unsigned tilew, tileh, tileb;
@@ -638,11 +638,11 @@ static int eg_surface_init_2d(struct
radeon_surface_manager *surf_man,
/* compute tile values */
tilew = 8;
tileh = 8;
- tileb = tilew * tileh * surf->bpe * surf->nsamples;
+ tileb = tilew * tileh * bpe * surf->nsamples;
/* slices per tile */
slice_pt = 1;
- if (tileb > surf->tile_split) {
- slice_pt = tileb / surf->tile_split;
+ if (tileb > tile_split) {
+ slice_pt = tileb / tile_split;
}
tileb = tileb / slice_pt;
@@ -653,15 +653,20 @@ static int eg_surface_init_2d(struct
radeon_surface_manager *surf_man,
mtileb = (mtilew / tilew) * (mtileh / tileh) * tileb;
if (!start_level) {
- surf->bo_alignment = MAX2(256, mtileb);
+ unsigned alignment = MAX2(256, mtileb);
+ surf->bo_alignment = MAX2(surf->bo_alignment, alignment);
+
+ if (offset) {
+ offset = ALIGN(offset, alignment);
+ }
}
/* build mipmap tree */
for (i = start_level; i <= surf->last_level; i++) {
- surf->level[i].mode = RADEON_SURF_MODE_2D;
- eg_surf_minify(surf, i, slice_pt, mtilew, mtileh, mtileb, offset);
- if (surf->level[i].mode == RADEON_SURF_MODE_1D) {
- return eg_surface_init_1d(surf_man, surf, offset, i);
+ level[i].mode = RADEON_SURF_MODE_2D;
+ eg_surf_minify(surf, level+i, bpe, i, slice_pt, mtilew, mtileh,
mtileb, offset);
+ if (level[i].mode == RADEON_SURF_MODE_1D) {
+ return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i);
}
/* level0 and first mipmap need to have alignment */
offset = surf->bo_size;
@@ -669,13 +674,6 @@ static int eg_surface_init_2d(struct
radeon_surface_manager *surf_man,
offset = ALIGN(offset, surf->bo_alignment);
}
}
-
- if ((surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) ==
- (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
- surf->stencil_offset = ALIGN(surf->bo_size, surf->bo_alignment);
- surf->bo_size = surf->stencil_offset + surf->bo_size / 4;
- }
-
return 0;
}
@@ -762,6 +760,51 @@ static int eg_surface_sanity(struct radeon_surface_manager
*surf_man,
return 0;
}
+static int eg_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man,
+ struct radeon_surface *surf)
+{
+ unsigned zs_flags = RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER;
+ int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags;
+ /* Old libdrm headers didn't have stencil_level in it. This prevents
crashes. */
+ struct radeon_surface_level tmp[RADEON_SURF_MAX_LEVEL];
+ struct radeon_surface_level *stencil_level =
+ (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level
: tmp;
+
+ r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0);
+ if (r)
+ return r;
+
+ if (is_depth_stencil) {
+ r = eg_surface_init_1d(surf_man, surf, stencil_level, 1,
+ surf->bo_size, 0);
+ surf->stencil_offset = stencil_level[0].offset;
+ }
+ return r;
+}
+
+static int eg_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man,
+ struct radeon_surface *surf)
+{
+ unsigned zs_flags = RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER;
+ int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags;
+ /* Old libdrm headers didn't have stencil_level in it. This prevents
crashes. */
+ struct radeon_surface_level tmp[RADEON_SURF_MAX_LEVEL];
+ struct radeon_surface_level *stencil_level =
+ (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level
: tmp;
+
+ r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe,
+ surf->tile_split, 0, 0);
+ if (r)
+ return r;
+
+ if (is_depth_stencil) {
+ r = eg_surface_init_2d(surf_man, surf, stencil_level, 1,
+ surf->stencil_tile_split, surf->bo_size, 0);
+ surf->stencil_offset = stencil_level[0].offset;
+ }
+ return r;
+}
+
static int eg_surface_init(struct radeon_surface_manager *surf_man,
struct radeon_surface *surf)
{
@@ -797,6 +840,7 @@ static int eg_surface_init(struct radeon_surface_manager
*surf_man,
}
surf->stencil_offset = 0;
+ surf->bo_alignment = 0;
/* check tiling mode */
switch (mode) {
@@ -807,10 +851,10 @@ static int eg_surface_init(struct radeon_surface_manager
*surf_man,
r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0);
break;
case RADEON_SURF_MODE_1D:
- r = eg_surface_init_1d(surf_man, surf, 0, 0);
+ r = eg_surface_init_1d_miptrees(surf_man, surf);
break;
case RADEON_SURF_MODE_2D:
- r = eg_surface_init_2d(surf_man, surf, 0, 0);
+ r = eg_surface_init_2d_miptrees(surf_man, surf);
break;
default:
return -EINVAL;
@@ -1058,6 +1102,7 @@ static int si_surface_init(struct radeon_surface_manager
*surf_man,
}
surf->stencil_offset = 0;
+ surf->bo_alignment = 0;
/* check tiling mode */
switch (mode) {
@@ -1068,10 +1113,10 @@ static int si_surface_init(struct
radeon_surface_manager *surf_man,
r = si_surface_init_linear_aligned(surf_man, surf, 0, 0);
break;
case RADEON_SURF_MODE_1D:
- r = eg_surface_init_1d(surf_man, surf, 0, 0);
+ r = eg_surface_init_1d_miptrees(surf_man, surf);
break;
case RADEON_SURF_MODE_2D:
- r = eg_surface_init_2d(surf_man, surf, 0, 0);
+ r = eg_surface_init_2d_miptrees(surf_man, surf);
break;
default:
return -EINVAL;
diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h
index bfee8ab..ed4b994 100644
--- a/radeon/radeon_surface.h
+++ b/radeon/radeon_surface.h
@@ -54,6 +54,7 @@
#define RADEON_SURF_SCANOUT (1 << 16)
#define RADEON_SURF_ZBUFFER (1 << 17)
#define RADEON_SURF_SBUFFER (1 << 18)
+#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT)
& RADEON_SURF_ ## field ## _MASK)
#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) <<
RADEON_SURF_ ## field ## _SHIFT)
@@ -102,6 +103,7 @@ struct radeon_surface {
uint32_t stencil_tile_split;
uint64_t stencil_offset;
struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL];
+ struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL];
};
struct radeon_surface_manager *radeon_surface_manager_new(int fd);
commit 77413e77b82a5d800c86b7d3b864d6cc797721c9
Author: Marek Olšák <mar...@gmail.com>
Date: Sun Sep 30 19:19:13 2012 +0200
radeon: don't force stencil tile split to 0
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 03b1c5d..c62cbf9 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -797,7 +797,6 @@ static int eg_surface_init(struct radeon_surface_manager
*surf_man,
}
surf->stencil_offset = 0;
- surf->stencil_tile_split = 0;
/* check tiling mode */
switch (mode) {
@@ -1059,7 +1058,6 @@ static int si_surface_init(struct radeon_surface_manager
*surf_man,
}
surf->stencil_offset = 0;
- surf->stencil_tile_split = 0;
/* check tiling mode */
switch (mode) {
commit b3d90bbc1d43bb11d8de25109f403b1b30533c34
Author: Marek Olšák <mar...@gmail.com>
Date: Sat Sep 29 15:10:33 2012 +0200
radeon: don't take the stencil-specific codepath for buffers without stencil
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 80b1505..03b1c5d 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -911,7 +911,7 @@ static int eg_surface_best(struct radeon_surface_manager
*surf_man,
* fmask buffer has different optimal value figure them out once we
* use it.
*/
- if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) {
+ if (surf->flags & RADEON_SURF_SBUFFER) {
/* assume 1 bytes for stencil, we optimize for stencil as stencil
* and depth shares surface values
*/
commit 2426a6a7112ae62755408a371831eddbe2d89d99
Author: Jesse Barnes <jbar...@virtuousgeek.org>
Date: Thu Sep 6 16:16:50 2012 -0700
libdrm: man page infrastructure and a few sample man pages
diff --git a/Makefile.am b/Makefile.am
index 256a8cc..8ecd9d9 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -49,7 +49,7 @@ if HAVE_EXYNOS
EXYNOS_SUBDIR = exynos
endif
-SUBDIRS = . $(LIBKMS_SUBDIR) $(INTEL_SUBDIR) $(NOUVEAU_SUBDIR)
$(RADEON_SUBDIR) $(OMAP_SUBDIR) $(EXYNOS_SUBDIR) tests include
+SUBDIRS = . $(LIBKMS_SUBDIR) $(INTEL_SUBDIR) $(NOUVEAU_SUBDIR)
$(RADEON_SUBDIR) $(OMAP_SUBDIR) $(EXYNOS_SUBDIR) tests include man
libdrm_la_LTLIBRARIES = libdrm.la
libdrm_ladir = $(libdir)
diff --git a/configure.ac b/configure.ac
index 51c1d2c..290362c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -35,6 +35,27 @@ AM_MAINTAINER_MODE([enable])
# Enable quiet compiles on automake 1.11.
m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
+if test x$LIB_MAN_SUFFIX = x ; then
+ LIB_MAN_SUFFIX=3
+fi
+if test x$LIB_MAN_DIR = x ; then
+ LIB_MAN_DIR='$(mandir)/man$(LIB_MAN_SUFFIX)'
+fi
+AC_SUBST([LIB_MAN_SUFFIX])
+AC_SUBST([LIB_MAN_DIR])
+
+MAN_SUBSTS="\
+ -e 's|__vendorversion__|\"\$(PACKAGE_STRING)\" |' \
+ -e 's|__projectroot__|\$(prefix)|g' \
+ -e 's|__apploaddir__|\$(appdefaultdir)|g' \
+ -e 's|__appmansuffix__|\$(APP_MAN_SUFFIX)|g' \
+ -e 's|__drivermansuffix__|\$(DRIVER_MAN_SUFFIX)|g' \
+ -e 's|__adminmansuffix__|\$(ADMIN_MAN_SUFFIX)|g' \
+ -e 's|__libmansuffix__|\$(LIB_MAN_SUFFIX)|g' \
+ -e 's|__miscmansuffix__|\$(MISC_MAN_SUFFIX)|g' \
+ -e 's|__filemansuffix__|\$(FILE_MAN_SUFFIX)|g'"
+AC_SUBST([MAN_SUBSTS])
+
# Check for programs
AC_PROG_CC
@@ -333,6 +354,7 @@ AC_CONFIG_FILES([
tests/vbltest/Makefile
include/Makefile
include/drm/Makefile
+ man/Makefile
libdrm.pc])
AC_OUTPUT
diff --git a/man/Makefile.am b/man/Makefile.am
new file mode 100644
index 0000000..73068e6
--- /dev/null
+++ b/man/Makefile.am
@@ -0,0 +1,11 @@
+libmandir = $(LIB_MAN_DIR)
+libman_PRE = drmAvailable.man \
+ drmHandleEvent.man \
+ drmModeGetResources.man
+libman_DATA = $(libman_PRE:man=@LIB_MAN_SUFFIX@)
+EXTRA_DIST = $(libman_PRE)
+CLEANFILE = $(libman_DATA)
+SUFFIXES = .$(LIB_MAN_SUFFIX) .man
+
+.man.$(LIB_MAN_SUFFIX):
+ $(AM_V_GEN)$(SED) $(MAN_SUBSTS) < $< > $@
diff --git a/man/drmAvailable.man b/man/drmAvailable.man
new file mode 100644
index 0000000..e1bb8dc
--- /dev/null
+++ b/man/drmAvailable.man
@@ -0,0 +1,25 @@
+.\" shorthand for double quote that works everywhere.
+.ds q \N'34'
+.TH drmAvailable __drivermansuffix__ __vendorversion__
+.SH NAME
+drmAvailable \- determine whether a DRM kernel driver has been loaded
+.SH SYNOPSIS
+.nf
+.B "#include <xf86drm.h>"
+
+.B "int drmAvailable(void);"
+.fi
+.SH DESCRIPTION
+This function allows the caller to determine whether a kernel DRM driver is
+loaded.
+
+.SH RETURN VALUE
+If a DRM driver is currently loaded, this function returns 1. Otherwise 0
+is returned.
+
+.SH REPORTING BUGS
+Bugs in this function should be reported to http://bugs.freedesktop.org under
+the "Mesa" product, with "Other" or "libdrm" as the component.
+
+.SH "SEE ALSO"
+drmOpen(__libmansuffix__)
diff --git a/man/drmHandleEvent.man b/man/drmHandleEvent.man
new file mode 100644
index 0000000..b98f417
--- /dev/null
+++ b/man/drmHandleEvent.man
@@ -0,0 +1,45 @@
+.\" shorthand for double quote that works everywhere.
+.ds q \N'34'
+.TH drmHandleEvent __drivermansuffix__ __vendorversion__
+.SH NAME
+drmHandleEvent \- read and process pending DRM events
+.SH SYNOPSIS
+.nf
+.B "#include <xf86drm.h>"
+
+.B "typedef struct _drmEventContext {"
+.BI " int version;"
+.BI " void (*vblank_handler)(int fd,"
+.BI " unsigned int sequence,"
+.BI " unsigned int tv_sec,"
+.BI " unsigned int tv_usec,"
+.BI " void *user_data);"
+.BI " void (*page_flip_handler)(int fd,"
+.BI " unsigned int sequence,"
+.BI " unsigned int tv_sec,"
+.BI " unsigned int tv_usec,"
+.BI " void *user_data);"
+.B "} drmEventContext, *drmEventContextPtr;"
+
+.B "int drmHandleEvent(int fd, drmEventContextPtr evctx);"
+.fi
+.SH DESCRIPTION
+This function will process outstanding DRM events on
+.I fd
+, which must be an open DRM device. This function should be called after
+the DRM file descriptor has polled readable; it will read the events and
+use the passed-in
+.I evctx
+structure to call function pointers with the parameters noted above.
+
+.SH RETURN VALUE
+Returns 0 on success, or if there is no data to read from the file descriptor.
+Returns -1 if the read on the file descriptor fails or returns less than a
+full event record.
+
+.SH REPORTING BUGS
+Bugs in this function should be reported to http://bugs.freedesktop.org under
+the "Mesa" product, with "Other" or "libdrm" as the component.
+
+.SH "SEE ALSO"
+drmModePageFlip(__libmansuffix__), drmWaitVBlank(__libmansuffix__)
diff --git a/man/drmModeGetResources.man b/man/drmModeGetResources.man
new file mode 100644
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