Felix, thank you very much - this is exactly what I needed! Also now found a "51192_Bolton_FCH_RRG.pdf" with slightly newer (but similar) info.
Dear friends, thank you so much for your kind help! Now this important work is completed for G505S and you're welcome to take a look at https://review.coreboot.org/c/coreboot/+/47852 . Maybe we can fix the IRQs for some other AMD fam15h boards in a similar way. Best regards, Mike Banon On Wed, Nov 18, 2020 at 2:14 AM Felix Held <[email protected]> wrote: > > Hi Mike! > > The PIRQ_MISC registers in the indirect I/O address space with 0xc00 > being the index register aren't IRQ numbers; those configuration bits. > To get an idea, have a look at the interrupt routing register chapter of > for example AMD publication number 45482 [1]. Not sure if that's the > exact one you'll need, but it should be a good starting point. > > Regards > Felix > > [1] https://www.amd.com/system/files/TechDocs/45482.pdf page 319 > _______________________________________________ > coreboot mailing list -- [email protected] > To unsubscribe send an email to [email protected] _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
