Hi Mike!
The PIRQ_MISC registers in the indirect I/O address space with 0xc00
being the index register aren't IRQ numbers; those configuration bits.
To get an idea, have a look at the interrupt routing register chapter of
for example AMD publication number 45482 [1]. Not sure if that's the
exact one you'll need, but it should be a good starting point.
Regards
Felix
[1] https://www.amd.com/system/files/TechDocs/45482.pdf page 319
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