jasonbu commented on code in PR #16344:
URL: https://github.com/apache/nuttx/pull/16344#discussion_r2081286731
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arch/arm/src/armv7-a/mmu.h:
##########
@@ -1351,21 +1351,44 @@ static inline void cp15_wrttb(unsigned int ttb)
****************************************************************************/
#ifndef CONFIG_ARCH_ROMPGTABLE
-static inline uint32_t *mmu_l1_pgtable(void)
+static inline uintptr_t *mmu_l1_getpgtable(void)
{
-#if defined(CONFIG_SMP) && defined(CONFIG_ARCH_ADDRENV)
+#ifdef CONFIG_ARCH_ADDRENV
uint32_t ttbr0;
uint32_t pgtable;
ttbr0 = CP15_GET(TTBR0);
pgtable = ttbr0 & TTBR0_BASE_MASK(0);
- return (uint32_t *)(pgtable - PGTABLE_BASE_PADDR + PGTABLE_BASE_VADDR);
+ return (uintptr_t *)(pgtable - PGTABLE_BASE_PADDR + PGTABLE_BASE_VADDR);
#else
- return (uint32_t *)PGTABLE_BASE_VADDR;
+ return (uintptr_t *)PGTABLE_BASE_VADDR;
#endif
}
#endif
+/****************************************************************************
+ * Name: mmu_l1_setpgtable
+ *
+ * Description:
+ * Update current L1 page table base address.
+ * The TTBR0 register contains the phys address for each cpu.
+ *
+ * Input Parameters:
+ * ttb - The new value of the TTBR0 register
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARCH_ROMPGTABLE
+# ifdef CONFIG_ARCH_ADDRENV
+static inline void mmu_l1_setpgtable(uintptr_t *ttb)
+{
+ cp15_wrttb((uint32_t)ttb | TTBR0_RGN_WBWA | TTBR0_IRGN0);
Review Comment:
did not put cp15_invalidate_tlbs inside mmu_l1_setpgtable,
because maybe we possible do ASID relative optimize, and don't have to
always invalid tlbs when set l1table.
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