[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Craig Topper via cfe-commits]

================
@@ -514,6 +514,78 @@ class RVInstJ<RISCVOpcode opcode, dag outs, dag ins, 
string opcodestr,
   let Inst{6-0} = opcode.Value;
 }
 
+//===----------------------------------------------------------------------===//
----------------
topperc wrote:

this should be in a MIPS vendor file

https://github.com/llvm/llvm-project/pull/117865
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits