[clang] [llvm] [RISC-V] Add support for MIPS P8700 CPU (PR #117865)

[Craig Topper via cfe-commits]

================
@@ -2710,6 +2713,45 @@ MachineInstr 
*RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
       .setMemRefs(MemI.memoperands())
       .setMIFlags(MemI.getFlags());
 }
+bool RISCVInstrInfo::isPairableLdStInstOpc(unsigned Opc) {
+  switch (Opc) {
+  default:
+    return false;
+  case RISCV::SH:
----------------
topperc wrote:

This list doesn't match what's supported in 
`RISCVLoadStoreOpt::tryConvertToLdStPair`

https://github.com/llvm/llvm-project/pull/117865
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