================ @@ -288,9 +288,9 @@ def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; def XER: SPR<1, "xer">, DwarfRegNum<[76]>; -// Carry bit. In the architecture this is really bit 0 of the XER register -// (which really is SPR register 1); this is the only bit interesting to a -// compiler. +// Carry bit. In the architecture this is really bit 2 of the 32-bit XER ---------------- stefanp-ibm wrote:
nit: The XER register is actually a 64 bit register. I realize that the first 32 bits are technically reserved (as well as a number of other bits like 35-43) but it is still a 64 bit register. In that way the carry bit becomes bit 34. I also looked above and it seems that we incorrectly document SPR as being one of a number of 32 bit registers. The issue is that some of the SPR are 32 bit and others are 64 bit. It really depends on which SPR we are looking at. I may be missing something here. Is there a history of the compiler assuming that all SPR are 32 bits? https://github.com/llvm/llvm-project/pull/77557 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
