================ @@ -288,9 +288,9 @@ def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; def XER: SPR<1, "xer">, DwarfRegNum<[76]>; -// Carry bit. In the architecture this is really bit 0 of the XER register -// (which really is SPR register 1); this is the only bit interesting to a -// compiler. +// Carry bit. In the architecture this is really bit 2 of the 32-bit XER ---------------- bzEq wrote:
> Is there a history of the compiler assuming that all SPR are 32 bits? The code was written more than a decade ago. I guess authors referenced *The PowerPC Compiler Writer’s Guide*. Figure 2-1 of the book shows XER, FPER, FPSCR are 32-bit width even under 64-bit environment. In appendix, there is > Carry bit Bit 2 in the Fixed-Point Exception Register (XER). https://github.com/llvm/llvm-project/pull/77557 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
