================ @@ -288,9 +288,9 @@ def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>; def XER: SPR<1, "xer">, DwarfRegNum<[76]>; -// Carry bit. In the architecture this is really bit 0 of the XER register -// (which really is SPR register 1); this is the only bit interesting to a -// compiler. +// Carry bit. In the architecture this is really bit 2 of the 32-bit XER ---------------- bzEq wrote:
I'll update it according to OpenPower's ISA, since it's more generally available. https://github.com/llvm/llvm-project/pull/77557 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
