compnerd added a comment. In D112890#3099256 <https://reviews.llvm.org/D112890#3099256>, @tschuett wrote:
> If I understand you correctly, I would need to pass something ala `-target > riscv-xx` to enable `__riscv_vector`. However, this is impossible because > the risk target is disabled. So I thing it is save what you are doing. Correct. You would need to invoke clang as `clang -target riscv64-unknown-linux-musl -march=rv64gv0p10 -menable-experimental-extensions` as a concrete example. At that point, you would be able to include `riscv_vector.h` for the declarations. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112890/new/ https://reviews.llvm.org/D112890 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
