compnerd added a comment. In D112890#3099208 <https://reviews.llvm.org/D112890#3099208>, @tschuett wrote:
> I am undecided between this may break something and I cannot use the risc-v > headers on an x86 machine. This fundamentally cannot break something outside of the RISC-V //target//, it is applicable to any and all hosts. However, the condition ensures that RISC-V support is not enabled when building the compiler. #ifndef __riscv_vector #error "Vector intrinsics require the vector extension." #endif `__riscv_vector` is in the implementation's namespace, so the user may not define this (it is defined by the compiler when targeting a RISCV core with the V extension). Trying to use `-target riscv32-unknown-*-*` or `-target riscv64-unknown-*-*` (not literally, but with a concrete value), will fail due to RISCV support being disabled in the build. That is, the header cannot be used on any machine when not targeting RISCV. Because RISCV is not enabled, it is safe to elide the header. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D112890/new/ https://reviews.llvm.org/D112890 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
