tschuett added a comment.

If I understand you correctly, I would need to pass something ala `-target 
riscv-xx` to  enable `__riscv_vector`. However, this is impossible because the 
risk target is disabled. So I thing it is save what you are doing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112890/new/

https://reviews.llvm.org/D112890

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