jrtc27 added inline comments.

================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:539
 
+let RegAltNameIndices = [ABIRegAltName] in {
+  foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
----------------
This needs to be coordinated with D95588; you both define GPR pairs for RV32 
but in different ways. There needs to be only one.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D93298/new/

https://reviews.llvm.org/D93298

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