jrtc27 added a comment.
The amount of duplication here really depresses me and is only going to get
worse once codegen is added, but TableGen isn't able to have operands that use
different register classes based on even HwMode, that I know of, and whilst you
could make use of multi classes to generate both versions of the instructions
you can't easily do that for patterns, so I don't know what the right answer is.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZdinx.td:193
+let Predicates = [HasStdExtZdinx, IsRV32] in {
+let DecoderNamespace = "RV32DZfinx" in {
+def FMADD_D_IN32X : FPFMADINX_rrr_frm<OPC_MADD, "fmadd.d", GPRPF64Op>,
----------------
Old extension name
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D93298/new/
https://reviews.llvm.org/D93298
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