achieveartificialintelligence updated this revision to Diff 379272.
achieveartificialintelligence marked an inline comment as done.
achieveartificialintelligence added a comment.
Add arch info
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D93298/new/
https://reviews.llvm.org/D93298
Files:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32i-invalid.s
Index: llvm/test/MC/RISCV/rv32i-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv32i-invalid.s
+++ llvm/test/MC/RISCV/rv32i-invalid.s
@@ -173,9 +173,9 @@
amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions)
fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point)
-fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer)
fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer)
fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer)
+fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer)
# Using floating point registers when integer registers are expected
addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/attribute-arch.s
===================================================================
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -72,6 +72,18 @@
.attribute arch, "rv32ifzfh"
# CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1"
+.attribute arch, "rv32izfinx"
+# CHECK: attribute 5, "rv32i2p0_zfinx0p1"
+
+.attribute arch, "rv32izdinx"
+# CHECK: attribute 5, "rv32i2p0_zfinx0p1_zdinx0p1"
+
+.attribute arch, "rv32izhinx"
+# CHECK: attribute 5, "rv32i2p0_zfinx0p1_zhinx0p1"
+
+.attribute arch, "rv32izhinxmin"
+# CHECK: attribute 5, "rv32i2p0_zfinx0p1_zhinxmin0p1"
+
.attribute arch, "rv32ivzvamo_zvlsseg"
# CHECK: attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10"
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -49,42 +49,42 @@
AssemblerPredicate<(all_of FeatureStdExtZfh),
"'Zfh' (Half-Precision Floating-Point)">;
-def FeatureExtZfinx
+def FeatureStdExtZfinx
: SubtargetFeature<"experimental-zfinx", "HasStdExtZfinx", "true",
"'Zfinx' (Float in Integer)">;
def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
- AssemblerPredicate<(all_of FeatureExtZfinx),
+ AssemblerPredicate<(all_of FeatureStdExtZfinx),
"'Zfinx' (Float in Integer)">;
-def FeatureExtZdinx
+def FeatureStdExtZdinx
: SubtargetFeature<"experimental-zdinx", "HasStdExtZdinx", "true",
"'Zdinx' (Double in Integer)",
- [FeatureExtZfinx]>;
+ [FeatureStdExtZfinx]>;
def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
- AssemblerPredicate<(all_of FeatureExtZdinx),
+ AssemblerPredicate<(all_of FeatureStdExtZdinx),
"'Zdinx' (Double in Integer)">;
-def FeatureExtZhinx
+def FeatureStdExtZhinx
: SubtargetFeature<"experimental-zhinx", "HasStdExtZhinx", "true",
"'Zhinx' (Half Float in Integer)",
- [FeatureExtZfinx]>;
+ [FeatureStdExtZfinx]>;
def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
- AssemblerPredicate<(all_of FeatureExtZhinx),
+ AssemblerPredicate<(all_of FeatureStdExtZhinx),
"'Zhinx' (Half Float in Integer)">;
-def FeatureExtZhinxmin
+def FeatureStdExtZhinxmin
: SubtargetFeature<"experimental-zhinxmin", "HasStdExtZhinxmin", "true",
"'Zhinxmin' (Half Float in Integer Minimal)",
- [FeatureExtZfinx]>;
+ [FeatureStdExtZfinx]>;
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
- AssemblerPredicate<(all_of FeatureExtZhinxmin),
+ AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
"'Zhinxmin' (Half Float in Integer Minimal)">;
// Some instructions belong to both the Zhinx and Zhinxmin.
// They should be enabled if either has been specified.
def HasStdExtZhinxOrZhinxmin
: Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
- AssemblerPredicate<(any_of FeatureExtZhinx, FeatureExtZhinxmin),
+ AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
"'Zhinx' (Half Float in Integer) or "
"'Zhinxmin' (Half Float in Integer Minimal)">;
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -64,6 +64,14 @@
Arch += "_v0p10";
if (STI.hasFeature(RISCV::FeatureStdExtZfh))
Arch += "_zfh0p1";
+ if (STI.hasFeature(RISCV::FeatureStdExtZfinx))
+ Arch += "_zfinx0p1";
+ if (STI.hasFeature(RISCV::FeatureStdExtZdinx))
+ Arch += "_zdinx0p1";
+ if (STI.hasFeature(RISCV::FeatureStdExtZhinx))
+ Arch += "_zhinx0p1";
+ if (STI.hasFeature(RISCV::FeatureStdExtZhinxmin))
+ Arch += "_zhinxmin0p1";
if (STI.hasFeature(RISCV::FeatureStdExtZba))
Arch += "_zba0p93";
if (STI.hasFeature(RISCV::FeatureStdExtZbb))
Index: llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
===================================================================
--- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -457,7 +457,7 @@
return MCDisassembler::Fail;
}
Insn = support::endian::read32le(Bytes.data());
- if (STI.getFeatureBits()[RISCV::FeatureExtZdinx] &&
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] &&
!STI.getFeatureBits()[RISCV::Feature64Bit]) {
LLVM_DEBUG(dbgs() << "Trying RV32Zdinx table (Double in Integer and"
"rv32)\n");
@@ -469,7 +469,7 @@
}
}
- if (STI.getFeatureBits()[RISCV::FeatureExtZfinx]) {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) {
LLVM_DEBUG(dbgs() << "Trying RVZfinx table (Float in Integer):\n");
// Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTableRVZfinx32, MI, Insn, Address, this,
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2121,6 +2121,10 @@
clearFeatureBits(RISCV::FeatureStdExtC, "c");
clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
clearFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
+ clearFeatureBits(RISCV::FeatureStdExtZfinx, "experimental-zfinx");
+ clearFeatureBits(RISCV::FeatureStdExtZdinx, "experimental-zdinx");
+ clearFeatureBits(RISCV::FeatureStdExtZhinx, "experimental-zhinx");
+ clearFeatureBits(RISCV::FeatureStdExtZhinxmin, "experimental-zhinxmin");
clearFeatureBits(RISCV::FeatureStdExtZba, "experimental-zba");
clearFeatureBits(RISCV::FeatureStdExtZbb, "experimental-zbb");
clearFeatureBits(RISCV::FeatureStdExtZbc, "experimental-zbc");
@@ -2184,6 +2188,14 @@
setFeatureBits(RISCV::FeatureStdExtZbt, "experimental-zbt");
else if (Ext == "zfh")
setFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfh");
+ else if (Ext == "zfinx")
+ setFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zfinx");
+ else if (Ext == "zdinx")
+ setFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zdinx");
+ else if (Ext == "zhinx")
+ setFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zhinx");
+ else if (Ext == "zhinxmin")
+ setFeatureBits(RISCV::FeatureStdExtZfh, "experimental-zhinxmin");
else if (Ext == "zvamo")
setFeatureBits(RISCV::FeatureStdExtZvamo, "experimental-zvamo");
else if (Ext == "zvlsseg")
@@ -2234,6 +2246,14 @@
formalArchStr = (Twine(formalArchStr) + "_v0p10").str();
if (getFeatureBits(RISCV::FeatureStdExtZfh))
formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
+ if (getFeatureBits(RISCV::FeatureStdExtZfinx))
+ formalArchStr = (Twine(formalArchStr) + "_zfinx0p1").str();
+ if (getFeatureBits(RISCV::FeatureStdExtZdinx))
+ formalArchStr = (Twine(formalArchStr) + "_zdinx0p1").str();
+ if (getFeatureBits(RISCV::FeatureStdExtZhinx))
+ formalArchStr = (Twine(formalArchStr) + "_zhinx0p1").str();
+ if (getFeatureBits(RISCV::FeatureStdExtZhinxmin))
+ formalArchStr = (Twine(formalArchStr) + "_zhinxmin0p1").str();
if (getFeatureBits(RISCV::FeatureStdExtZba))
formalArchStr = (Twine(formalArchStr) + "_zba0p93").str();
if (getFeatureBits(RISCV::FeatureStdExtZbb))
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