jrtc27 added a comment. In D98616#2626094 <https://reviews.llvm.org/D98616#2626094>, @jrtc27 wrote:
> In D98616#2626093 <https://reviews.llvm.org/D98616#2626093>, @kito-cheng > wrote: > >> GCC use `vr` for vector register and `vm` for vector mask register. > > How does that even work? Aren't multi character strings a set of options? Hm, apparently multi-character constraints already exist. Not a fan of it as it parses like "vector or register/memory" to me but if that's how GCC needs to internally model its instructions then we have to copy that... Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D98616/new/ https://reviews.llvm.org/D98616 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
