[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

[Hsiangkai Wang via Phabricator via cfe-commits]

HsiangKai created this revision.
HsiangKai added reviewers: craig.topper, frasercrmck, rogfer01.
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sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, 
brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, 
niosHD, sabuasal, simoncook, johnrusso, rbar, asb.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98616

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c


Index: clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v \
+// RUN:     -O2 -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN:     -O2 -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+
+// Test RISC-V V-extension specific inline assembly constraints.
+#include <riscv_vector.h>
+
+void test_v_reg() {
+  asm volatile(
+      "vsetvli x1, x0, e32,m2,tu,mu\n"
+      "vadd.vv v1, v2, v3, v0.t"
+      :
+      :
+      : "v1", "x1");
+// CHECK-LABEL: define{{.*}} @test_v_reg
+// CHECK: "~{v1},~{x1}"
+}
+
+vint32m1_t test_v(vint32m1_t a, vint32m1_t b) {
+// CHECK-LABEL: define{{.*}} @test_v
+// CHECK: %0 = tail call <vscale x 2 x i32> asm sideeffect "vadd.vv $0, $1, 
$2", "=v,v,v"(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
+  vint32m1_t ret;
+  asm volatile ("vadd.vv %0, %1, %2" : "=v"(ret) : "v"(a), "v"(b));
+  return ret;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -31,7 +31,13 @@
       "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
       "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
       "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
-      "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
+      "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+
+      // Vector registers
+      "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+      "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
+      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"};
   return llvm::makeArrayRef(GCCRegNames);
 }
 
@@ -81,6 +87,10 @@
     // An address that is held in a general-purpose register.
     Info.setAllowsMemory();
     return true;
+  case 'v':
+    // A vector register.
+    Info.setAllowsRegister();
+    return true;
   }
 }
 



Index: clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v \
+// RUN:     -O2 -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN:     -O2 -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+
+// Test RISC-V V-extension specific inline assembly constraints.
+#include <riscv_vector.h>
+
+void test_v_reg() {
+  asm volatile(
+      "vsetvli x1, x0, e32,m2,tu,mu\n"
+      "vadd.vv v1, v2, v3, v0.t"
+      :
+      :
+      : "v1", "x1");
+// CHECK-LABEL: define{{.*}} @test_v_reg
+// CHECK: "~{v1},~{x1}"
+}
+
+vint32m1_t test_v(vint32m1_t a, vint32m1_t b) {
+// CHECK-LABEL: define{{.*}} @test_v
+// CHECK: %0 = tail call <vscale x 2 x i32> asm sideeffect "vadd.vv $0, $1, $2", "=v,v,v"(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
+  vint32m1_t ret;
+  asm volatile ("vadd.vv %0, %1, %2" : "=v"(ret) : "v"(a), "v"(b));
+  return ret;
+}
Index: clang/lib/Basic/Targets/RISCV.cpp
===================================================================
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -31,7 +31,13 @@
       "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
       "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
       "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
-      "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
+      "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+
+      // Vector registers
+      "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+      "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
+      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"};
   return llvm::makeArrayRef(GCCRegNames);
 }
 
@@ -81,6 +87,10 @@
     // An address that is held in a general-purpose register.
     Info.setAllowsMemory();
     return true;
+  case 'v':
+    // A vector register.
+    Info.setAllowsRegister();
+    return true;
   }
 }
 

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