[PATCH] D98616: [RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added a comment.

GCC use `vr` for vector register and `vm` for vector mask register.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D98616/new/

https://reviews.llvm.org/D98616

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