sdesmalen added a comment.
Functionally the patch looks good, but the title suggests this adds full
inline-asm support for SVE (which would require the ACLE types proposed in
D62960 <https://reviews.llvm.org/D62960>, as well as other changes), where this
patch only adds support to specify SVE registers in the clobber list.
================
Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:4
+long test_z0_p0()
+{
+ long t;
----------------
nit: there is no reason to have a different code-style for code and tests
(curly brace is on next line here).
Maybe run this through clang-format?
================
Comment at: clang/test/CodeGen/aarch64-sve-inline-asm.c:7
+
+ asm volatile(
+ "ptrue p0.d\n"
----------------
nit: The asm/instructions here don't really need to make sense (as in: they are
not executed), so you can combine all three tests into one, as long as the
instructions are valid and z0, p0, z31 and z15 are used.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D64739/new/
https://reviews.llvm.org/D64739
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