> On Jan 31, 2019, at 3:02 PM, Jay Jaeger via cctalk <cctalk@classiccmp.org>
> wrote:
>
> On 1/31/2019 12:02 PM, Fritz Mueller via cctalk wrote:
>
>
>>
>> I don't actually have anything that uses the M8110; I am mostly interested
>> in that one to understand how it co-evolved with the parity changes in the
>> CPU (sometimes its easier to understand if you can see both sides).
>>
>> cheers (and thanks again!),
>> --FritzM.
>>
>
> Well, the short answer is the same: it seems to have been an absolute
> mess. So bad DEC eventually threw in the towel on it, apparently, and
> moved on and created the M8120. Perhaps foreshadowing the mess that
> MITS had with its first 4K dynamic memory board. ;)
>
> So, if you have one in there, you don't want it in any memory you will
> be addressing. I'd probably pull it, or at least put it way up high
> with a gap before it.
Interesting. By the way, a gap won't make any difference for RSTS. When it
scans for memory, it examines the entire address space. So whether memory is
contiguous or not, it will all be seen if it appears to be working. You can
disable it (via memory options in DEFAULT) if you need to.
> The parity change in the CPU was to change parity errors from vectoring
> thru location 4 to vector through 114.
>
> My 1972 and 1973 11/45 processor handbooks do not mention location 114,
> just location 4.
>
> My 1976 pdp11/04/05/10/35/40/45 identify 114 as the vector for memory
> system errors. So software (and diagnostics) from sometime after 1973
> would presumably expect that.
RSTS certainly requires that, yes.
paul
