On 03/22/2018 05:47 AM, Zane Healy via cctalk wrote:
I’ve been working on updating my DEC emulation site, that includes the FPGA
section. That might help you find some, I’m sure that I have plenty of gaps.
http://www.avanthar.com/healyzh/decemulation/pdp_fpga.html
Zane
Here is mine for the list, a PDP-1 (and some optional PDP-1D features)
in Verilog:
https://github.com/Jside/pdp1
It is a behavioral implementation rather than a gate-by-gate one.
So it is easy to read and debug but not accurate in the instruction
"pipeline" or timings.
- Jan
