On 21/03/18, Zane Healy via cctalk wrote: > I’ve been working on updating my DEC emulation site, that includes the FPGA > section. That might help you find some, I’m sure that I have plenty of gaps. > > http://www.avanthar.com/healyzh/decemulation/pdp_fpga.html >
I'd like to add mine to the list: I've done a PDP-6 (not tested very much, but that should change soon): https://github.com/aap/pdp6/tree/master/verilog ...and am currently working on a KA10: https://github.com/aap/pdp10 My goal is to stay as close to the original schematics as possible. That means I'm simulating delay elements with counters and stuff like that. Also note that these two projects are the only experience with HDLs that I have. Don't expect them to be very professional. aap
