On 11/19/2017 08:54 AM, Noel Chiappa via cctalk wrote: > > From: Allison > > > simple 16 data, 24 address likely 6 lines for basic control plus others > > your up to 50+ lines > > I would seriously consider shared data/address lines, like on the QBUS. It > doesn't add _that_ much complexity to share the lines (I did a slave device > using only 74xxx parts, and it was dead simple - probably a goal of the > designers), and it will really drop the pin count. The speed impact is not > too bad - on reads, where the address and data naturally happen at different > times, it can be none. > > Noel QBUS is wrapped around a subset of PDP11 and the unique processors made to fit it. The problem is carries is every card has to demux the bus that has hardware cost on every card. if the CPU doesn't initially multiplex the CPU card carries the weight of creating that muxed bus. Dec had a full set of unique devices to do this. I may add that things like PDP-11 with read before write adding its own special set of issues for peripherals.
The problem with multiplexed buses is speed cost. You have to use fast parts that are compatible with the bus levels and the bus may have to be artfully constructed to avoid issues that occur when operating at high speed. The other is how do you multiplex for example look and devices like 8085, 8088, z80 and 6502 the timing overheard is different and the bus could even contradict something like the 8085/8088 which is already multiplexed. The bottom line is for every bus you have to get on and off with devices to buffer and possibly latch signals. The more you use the less card there is for other things and likely the mode complex the card and its related timings will be. Its s solution when pins and their cost is more important that logic. The old saw Speed, quality, price pick any two applies. Added complexity will add cost or slow development and maybe even add bugs. Allison
