Perhaps Oberon required something faster than the 70ns - 85ns tRC read cycle / tWC write cycle times supported by the Micron cellular RAM running in asynchronous mode on the Nexys 2 - presumably because the data path is only 16 bits?
That said, most "retro" computing would, I expect, be perfectly happy with that kind of cycle time and bus width, yes? And the implementation in this asynch. mode is very very easy - classic SRAM interface signals. Looks like the Nexys 3 and Nexys 4 boards have cellular RAM like this as well. JRJ On 11/23/2015 8:47 PM, William Maddox wrote: > [Yahoo's webmail client garbled the last link -- resending] > The revived 2013 re-issue of Niklaus Wirth's Oberon system is a joy to > behold. If you've never heard of Oberon before, it is a minimalistic > education-oriented language and operating system designed after Wirth had > taken a (second) sabattical at PARC in the 80's. > The new version runs on a custom RISC processor, implemented in an FPGA, > instead of the NS3032 in the orginal Ceres workstations. Originally, it > required a Digilent "Spartan 3 Starter Kit" with a custom-built daughterboard > providing a few additional connectors. This board is no longer made, > however, and no other FPGA development board appears to provide the 32-bit > wide fast SRAM the Oberon CPU required. > Recently, a new board, the OberonStation, has come onto the market that was > designed specifically for Oberon, and will boot up Oberon 2013 out of the > box. It also looks like an excellent platform for other retro-style FPGA > CPU designs that want to stay away from complex SDRAM controllers and the > caches they like to feed. > > My OberonStation arrived a couple of days ago, and it's really amazing to see > what can be done with a hardware and software stack that is small enough to > actually read and understand. > https://www.inf.ethz.ch/personal/wirth/ > > http://www.projectoberon.com/ > http://oberonstation.x10.mx/ >
