> > Note that some version of L4 consumed 4 TLB entries for one IPC: 2 > that were the same for every kernel interrupt. 1 for the source > thread. 1 for the destination thread. It is hard to do better than
Using a bigger ('super') page the kernel interrupt stuff can be mapped
using only 1 TLB entry no ?
TLB entries are a fairly scarce resource in some of the smaller CPUs. A
lot of CPUs also use so called 'soft refill mechanism' meaning the OS is
responsible for managing the TLB. Obviously the TLB refill handler is
heavily optimized, but still you want to be able to map the complete working
set using TLB entries.
Cheers,
Peter (p2).
--
goa is a state of mind
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