An important correction to the information provided by Jon Perryman regarding how the branch address in the BRCT, BRCTG and BRCTH instructions is computed.
The RI field is a signed binary integer value which represents the number of halfwords which is added to the address of the instruction itself, NOT the address field of the PSW, to generate the branch address. This type of address computation is the same for all Relative Addressing instructions, not just for branching instructions, when operand(s) locations are expressed using Relative Addressing (for example, the second operand of the LOAD RELATIVE LONG instruction). In the general (common) case of instruction sequencing and execution, the address field of the PSW and the address of the instruction itself are the same. However, in the case of the EXECUTE instruction, the address field of the PSW refers to the location of the EXECUTE instruction, NOT the location of the instruction to be EXECUTEd (i.e., the EXECUTE "target" address). On Wed, Feb 26, 2025 at 4:26 PM Jon Perryman <jperr...@pacbell.net> wrote: > > On Wednesday, February 26, 2025 at 05:33:06 AM PST, Joseph Reichman < > reichman...@gmail.com> wrote:> The BCTG instruction is at location 2E60> > LONGDISP is at location A0 so the displacement is 2E60 - A0 = 2DC0 > > Joseph, > > You confused BCTG with JCTG. BCT and BCTG use an offset from a base > register (calculated from USING label). > > JCTG & JCT are relative instructions based on the current PSW. Your > calculation for a relative instruction is backwards (not AO-LONGDISP). If > you used JCTG, then LONGDISP-PSW=A0-2E60= -2DC0. > > As for the G in BCTG, it means registers not used for addressing will be > 64 bit instead of 32 bit. In this case, the count register will be 64 bit. > Registers used for addressing are controlled by SETAMODE. >
