Hello, I am still trying to run OpenBSD on Orange Pi One Plus(Allwinner H6). At least following fixes are needed.
- add AXP805 support to axppmic - add DW-UART FIFO fix to com (previously posted at https://www.mail-archive.com/arm@openbsd.org/msg02146.html but not tested on Rockchip and Marvell yet) - add Allwinner H6 USB-PHY support to ehci_fdt - add Allwinner H6 clock/reset setting to sxiccmu On Orange Pi One Plus, AXP805 PMIC can access from I2C and RSB. Linux uses RSB but U-Boot (2021.10) DTB uses I2C. sxirsb has "early 1" option to initialize before other devices, so sxitwi needs same thing. Even if these fix are applied, dwxe cannot find ethernet PHY (RT8211). Orange Pi One Plus' Schematics and DTB defines PHY address as 0x01, but actually probed at 0x00 (MII broadcast) and 0x07. We have to modify DTB or take measures such misconfiguration. type 0x2 pa 0x40000000 va 0x40000000 pages 0x4000 attr 0x8 type 0x7 pa 0x44000000 va 0x44000000 pages 0x3ef5 attr 0x8 type 0x9 pa 0x47ef5000 va 0x47ef5000 pages 0x16 attr 0x8 type 0x7 pa 0x47f0b000 va 0x47f0b000 pages 0x32eda attr 0x8 type 0x2 pa 0x7ade5000 va 0x7ade5000 pages 0x9 attr 0x8 type 0x7 pa 0x7adee000 va 0x7adee000 pages 0x1 attr 0x8 type 0x2 pa 0x7adef000 va 0x7adef000 pages 0x100 attr 0x8 type 0x1 pa 0x7aeef000 va 0x7aeef000 pages 0x2a attr 0x8 type 0x4 pa 0x7af19000 va 0x7af19000 pages 0x8 attr 0x8 type 0x6 pa 0x7af21000 va 0x1b0a748000 pages 0x4 attr 0x8000000000000008 type 0x4 pa 0x7af25000 va 0x7af25000 pages 0x1 attr 0x8 type 0x6 pa 0x7af26000 va 0x1b0a74d000 pages 0x4 attr 0x8000000000000008 type 0x4 pa 0x7af2a000 va 0x7af2a000 pages 0xc attr 0x8 type 0x2 pa 0x7af36000 va 0x7af36000 pages 0x501a attr 0x8 type 0x5 pa 0x7ff50000 va 0x1b0f777000 pages 0x10 attr 0x8000000000000008 type 0x2 pa 0x7ff60000 va 0x7ff60000 pages 0xa0 attr 0x8 [ using 8879376 bytes of bsd ELF symbol table ] Copyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2021 OpenBSD. All rights reserved. https://www.OpenBSD.org OpenBSD 7.0-current (GENERIC.MP) #60: Sat Nov 27 05:43:28 JST 2021 u...@openbsd-current-vm.uaa.org.uk:/usr/src/sys/arch/arm64/compile/GENERIC.MP real mem = 987557888 (941MB) avail mem = 918450176 (875MB) random: boothowto does not indicate good seed mainbus0 at root: OrangePi One Plus psci0 at mainbus0: PSCI 1.1, SMCCC 1.2 cpu0 at mainbus0 mpidr 0: ARM Cortex-A53 r0p4 cpu0: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache cpu0: 512KB 64b/line 16-way L2 cache cpu0: CRC32,SHA2,SHA1,AES+PMULL,ASID16 cpu1 at mainbus0 mpidr 1: ARM Cortex-A53 r0p4 cpu1: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache cpu1: 512KB 64b/line 16-way L2 cache cpu1: CRC32,SHA2,SHA1,AES+PMULL,ASID16 cpu2 at mainbus0 mpidr 2: ARM Cortex-A53 r0p4 cpu2: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache cpu2: 512KB 64b/line 16-way L2 cache cpu2: CRC32,SHA2,SHA1,AES+PMULL,ASID16 cpu3 at mainbus0 mpidr 3: ARM Cortex-A53 r0p4 cpu3: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 D-cache cpu3: 512KB 64b/line 16-way L2 cache cpu3: CRC32,SHA2,SHA1,AES+PMULL,ASID16 efi0 at mainbus0: UEFI 2.8 efi0: Das U-Boot rev 0x20211000 apm0 at mainbus0 "display-engine" at mainbus0 not configured "osc24M_clk" at mainbus0 not configured "pmu" at mainbus0 not configured agtimer0 at mainbus0: 24000 kHz simplebus0 at mainbus0: "soc" sxisyscon0 at simplebus0 sxiccmu0 at simplebus0 sxisid0 at simplebus0 sxipio0 at simplebus0: 108 pins ampintc0 at simplebus0 nirq 192, ncpu 4 ipi: 0, 1: "interrupt-controller" sxiccmu1 at simplebus0 sxipio1 at simplebus0: 16 pins sxitwi0 at simplebus0 iic0 at sxitwi0 axppmic0 at iic0 addr 0x36: AXP805 "bus" at simplebus0 not configured "video-codec" at simplebus0 not configured "gpu" at simplebus0 not configured "crypto" at simplebus0 not configured "dma-controller" at simplebus0 not configured "mailbox" at simplebus0 not configured "iommu" at simplebus0 not configured sximmc0 at simplebus0 sdmmc0 at sximmc0: 4-bit, sd high-speed, mmc high-speed, dma com0 at simplebus0: DesignWare APB UART, no fifo com0: console dwxe0 at simplebus0: address 02:07:11:b5:5a:5a dwxe0: no PHY found! "usb" at simplebus0 not configured "phy" at simplebus0 not configured ehci0 at simplebus0 usb0 at ehci0: USB revision 2.0 uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1 ohci0 at simplebus0: version 1.0 ehci1 at simplebus0 usb1 at ehci1: USB revision 2.0 uhub1 at usb1 configuration 1 interface 0 "Generic EHCI root hub" rev 2.00/1.00 addr 1 ohci1 at simplebus0: version 1.0 "hdmi" at simplebus0 not configured "hdmi-phy" at simplebus0 not configured "tcon-top" at simplebus0 not configured "lcd-controller" at simplebus0 not configured "rtc" at simplebus0 not configured sxidog0 at simplebus0 "interrupt-controller" at simplebus0 not configured "ir" at simplebus0 not configured "thermal-sensor" at simplebus0 not configured gpio0 at sxipio0: 32 pins gpio1 at sxipio0: 32 pins gpio2 at sxipio0: 32 pins gpio3 at sxipio0: 32 pins gpio4 at sxipio0: 32 pins gpio5 at sxipio0: 32 pins gpio6 at sxipio0: 32 pins gpio7 at sxipio0: 32 pins gpio8 at sxipio1: 32 pins gpio9 at sxipio1: 32 pins usb2 at ohci0: USB revision 1.0 uhub2 at usb2 configuration 1 interface 0 "Generic OHCI root hub" rev 1.00/1.00 addr 1 usb3 at ohci1: USB revision 1.0 uhub3 at usb3 configuration 1 interface 0 "Generic OHCI root hub" rev 1.00/1.00 addr 1 "connector" at mainbus0 not configured "ext_osc32k_clk" at mainbus0 not configured gpioleds0 at mainbus0: "orangepi:red:power" "vcc5v" at mainbus0 not configured "gmac-3v3" at mainbus0 not configured "binman" at mainbus0 not configured dt: 451 probes scsibus0 at sdmmc0: 2 targets, initiator 0 sd0 at scsibus0 targ 1 lun 0: <SD/MMC, SD16G, 0030> removable sd0: 14784MB, 512 bytes/sector, 30277632 sectors umass0 at uhub1 port 1 configuration 1 interface 0 "USB Storage USB Storage" rev 2.00/14.04 addr 2 umass0: using SCSI over Bulk-Only scsibus1 at umass0: 2 targets, initiator 0 sd1 at scsibus1 targ 1 lun 0: <Generic, STORAGE DEVICE, 1404> removable sd1: 14768MB, 512 bytes/sector, 30244864 sectors vscsi0 at root scsibus2 at vscsi0: 256 targets softraid0 at root scsibus3 at softraid0: 256 targets root on sd0a (225f855485964206.a) swap on sd0b dump on sd0b WARNING: CHECK AND RESET THE DATE! warning: /dev/console does not exist init: not found panic: no init Stopped at panic+0x160 [/usr/src/sys/kern/subr_prf.c:202]: cmp w21, #0 x0 TID PID UID PRFLAGS PFLAGS CPU COMMAND 478035 7254 0 0x14000 0x200 1 zerothread *200532 1 0 0 0 2 swapper db_enter() at panic+0x15c [/usr/src/sys/kern/subr_prf.c:231] panic() at start_init+0x2a0 [/usr/src/sys/kern/init_main.c:761] start_init() at proc_trampoline+0x10 https://www.openbsd.org/ddb.html describes the minimum info required in bug reports. Insufficient info makes it difficult to find and fix bugs. ddb{2}> -- SASANO Takayoshi (JG1UAA) <u...@mx5.nisiq.net> Index: arch/arm64/conf/GENERIC =================================================================== RCS file: /cvs/src/sys/arch/arm64/conf/GENERIC,v retrieving revision 1.214 diff -u -p -u -p -r1.214 GENERIC --- arch/arm64/conf/GENERIC 22 Nov 2021 20:25:50 -0000 1.214 +++ arch/arm64/conf/GENERIC 26 Nov 2021 20:44:38 -0000 @@ -295,7 +295,7 @@ sdmmc* at sximmc? # SD/MMC bus sxisid* at fdt? early 1 sxisyscon* at fdt? early 1 # System controller sxitemp* at fdt? # Temperature sensor -sxitwi* at fdt? # I2C controller +sxitwi* at fdt? early 1 # I2C controller iic* at sxitwi? # I2C bus dwxe* at fdt? @@ -481,6 +481,7 @@ uk* at scsibus? # I2C devices abcrtc* at iic? # Abracon x80x RTC +axppmic* at iic? # AXP80x PMIC cwfg* at iic? # CellWise CW201x fuel gauge dsxrtc* at iic? # DS3231 RTC escodec* at iic? # ES8316 audio codec Index: dev/fdt/axppmic.c =================================================================== RCS file: /cvs/src/sys/dev/fdt/axppmic.c,v retrieving revision 1.11 diff -u -p -u -p -r1.11 axppmic.c --- dev/fdt/axppmic.c 24 Oct 2021 17:52:26 -0000 1.11 +++ dev/fdt/axppmic.c 26 Nov 2021 20:44:39 -0000 @@ -293,6 +293,7 @@ struct axppmic_device axppmic_devices[] { "x-powers,axp221", "AXP221", axp221_regdata, axp221_sensdata }, { "x-powers,axp223", "AXP223", axp221_regdata, axp221_sensdata }, { "x-powers,axp803", "AXP803", axp803_regdata, axp803_sensdata }, + { "x-powers,axp805", "AXP805", axp806_regdata }, { "x-powers,axp806", "AXP806", axp806_regdata }, { "x-powers,axp809", "AXP809", axp809_regdata, axp221_sensdata } }; @@ -491,8 +492,10 @@ axppmic_attach_common(struct axppmic_sof sc->sc_sensdata = device->sensdata; /* Switch AXP806 into master or slave mode. */ - if (strcmp(name, "x-powers,axp806") == 0) { - if (OF_getproplen(node, "x-powers,master-mode") == 0) { + if (strcmp(name, "x-powers,axp805") == 0 || + strcmp(name, "x-powers,axp806") == 0) { + if (OF_getproplen(node, "x-powers,master-mode") == 0 || + OF_getproplen(node, "x-powers,self-working-mode") == 0) { axppmic_write_reg(sc, AXP806_REG_ADDR_EXT, AXP806_REG_ADDR_EXT_MASTER_MODE); } else { Index: dev/fdt/com_fdt.c =================================================================== RCS file: /cvs/src/sys/dev/fdt/com_fdt.c,v retrieving revision 1.6 diff -u -p -u -p -r1.6 com_fdt.c --- dev/fdt/com_fdt.c 24 Oct 2021 17:52:26 -0000 1.6 +++ dev/fdt/com_fdt.c 26 Nov 2021 20:44:39 -0000 @@ -33,8 +33,6 @@ #include <dev/ofw/ofw_clock.h> #include <dev/ofw/ofw_pinctrl.h> -#define com_usr 31 /* Synopsys DesignWare UART */ - int com_fdt_match(struct device *, void *, void *); void com_fdt_attach(struct device *, struct device *, void *); int com_fdt_intr_designware(void *); @@ -144,8 +142,10 @@ com_fdt_attach(struct device *parent, st sc->sc_reg_shift = OF_getpropint(faa->fa_node, "reg-shift", shift); if (OF_is_compatible(faa->fa_node, "snps,dw-apb-uart") || - OF_is_compatible(faa->fa_node, "marvell,armada-38x-uart")) + OF_is_compatible(faa->fa_node, "marvell,armada-38x-uart")) { + sc->sc_uarttype = COM_UART_DW_APB; intr = com_fdt_intr_designware; + } if (OF_is_compatible(faa->fa_node, "ti,omap3-uart") || OF_is_compatible(faa->fa_node, "ti,omap4-uart")) Index: dev/fdt/ehci_fdt.c =================================================================== RCS file: /cvs/src/sys/dev/fdt/ehci_fdt.c,v retrieving revision 1.7 diff -u -p -u -p -r1.7 ehci_fdt.c --- dev/fdt/ehci_fdt.c 24 Oct 2021 17:52:26 -0000 1.7 +++ dev/fdt/ehci_fdt.c 26 Nov 2021 20:44:39 -0000 @@ -174,6 +174,7 @@ struct ehci_phy ehci_phys[] = { { "allwinner,sun8i-h3-usb-phy", sun4i_phy_init }, { "allwinner,sun8i-r40-usb-phy", sun4i_phy_init }, { "allwinner,sun8i-v3s-usb-phy", sun4i_phy_init }, + { "allwinner,sun50i-h6-usb-phy", sun4i_phy_init }, { "allwinner,sun50i-a64-usb-phy", sun4i_phy_init }, { "allwinner,sun9i-a80-usb-phy", sun9i_phy_init }, }; @@ -274,6 +275,7 @@ sun4i_phy_init(struct ehci_fdt_softc *sc */ if (OF_is_compatible(node, "allwinner,sun8i-h3-usb-phy") || OF_is_compatible(node, "allwinner,sun8i-r40-usb-phy") || + OF_is_compatible(node, "allwinner,sun50i-h6-usb-phy") || OF_is_compatible(node, "allwinner,sun50i-a64-usb-phy")) { val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810); val &= ~(1 << 1); Index: dev/fdt/sxiccmu.c =================================================================== RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v retrieving revision 1.29 diff -u -p -u -p -r1.29 sxiccmu.c --- dev/fdt/sxiccmu.c 24 Oct 2021 17:52:27 -0000 1.29 +++ dev/fdt/sxiccmu.c 26 Nov 2021 20:44:39 -0000 @@ -1311,15 +1311,30 @@ sxiccmu_h3_r_get_frequency(struct sxiccm return 0; } + +#define H6_AHB3_CFG_REG 0x051c +#define H6_AHB3_CLK_FACTOR_N(x) (((x) >> 8) & 0x3) +#define H6_AHB3_CLK_FACTOR_M(x) (((x) >> 0) & 0x3) + uint32_t sxiccmu_h6_get_frequency(struct sxiccmu_softc *sc, uint32_t idx) { + uint32_t reg, m, n; + uint32_t freq; + switch (idx) { case H6_CLK_PLL_PERIPH0: /* Not hardcoded, but recommended. */ return 600000000; case H6_CLK_PLL_PERIPH0_2X: return sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0) * 2; + case H6_CLK_AHB3: + reg = SXIREAD4(sc, H6_AHB3_CFG_REG); + /* assume PLL_PERIPH0 source */ + freq = sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0); + m = H6_AHB3_CLK_FACTOR_M(reg) + 1; + n = 1 << H6_AHB3_CLK_FACTOR_N(reg); + return freq / (m * n); case H6_CLK_APB2: /* XXX Controlled by a MUX. */ return 24000000; Index: dev/fdt/sxiccmu_clocks.h =================================================================== RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v retrieving revision 1.31 diff -u -p -u -p -r1.31 sxiccmu_clocks.h --- dev/fdt/sxiccmu_clocks.h 29 Sep 2020 21:05:05 -0000 1.31 +++ dev/fdt/sxiccmu_clocks.h 26 Nov 2021 20:44:39 -0000 @@ -408,6 +408,7 @@ struct sxiccmu_ccu_bit sun8i_h3_r_gates[ #define H6_CLK_PLL_PERIPH0 3 #define H6_CLK_PLL_PERIPH0_2X 4 +#define H6_CLK_AHB3 25 #define H6_CLK_APB1 26 #define H6_CLK_APB2 27 #define H6_CLK_MMC0 64 @@ -420,8 +421,12 @@ struct sxiccmu_ccu_bit sun8i_h3_r_gates[ #define H6_CLK_BUS_UART1 71 #define H6_CLK_BUS_UART2 72 #define H6_CLK_BUS_UART3 73 +#define H6_CLK_BUS_EMAC 84 #define H6_CLK_USB_OHCI0 104 +#define H6_CLK_USB_PHY0 105 +#define H6_CLK_USB_PHY1 106 #define H6_CLK_USB_OHCI3 107 +#define H6_CLK_USB_PHY3 108 #define H6_CLK_BUS_OHCI0 111 #define H6_CLK_BUS_OHCI3 112 #define H6_CLK_BUS_EHCI0 113 @@ -440,8 +445,12 @@ struct sxiccmu_ccu_bit sun50i_h6_gates[] [H6_CLK_BUS_UART1] = { 0x090c, 1, H6_CLK_APB2 }, [H6_CLK_BUS_UART2] = { 0x090c, 2, H6_CLK_APB2 }, [H6_CLK_BUS_UART3] = { 0x090c, 3, H6_CLK_APB2 }, + [H6_CLK_BUS_EMAC] = { 0x097c, 0, H6_CLK_AHB3 }, [H6_CLK_USB_OHCI0] = { 0x0a70, 31 }, + [H6_CLK_USB_PHY0] = { 0x0a70, 29 }, + [H6_CLK_USB_PHY1] = { 0x0a74, 29 }, [H6_CLK_USB_OHCI3] = { 0x0a7c, 31 }, + [H6_CLK_USB_PHY3] = { 0x0a7c, 29 }, [H6_CLK_BUS_OHCI0] = { 0x0a8c, 0 }, [H6_CLK_BUS_OHCI3] = { 0x0a8c, 3 }, [H6_CLK_BUS_EHCI0] = { 0x0a8c, 4 }, @@ -451,10 +460,12 @@ struct sxiccmu_ccu_bit sun50i_h6_gates[] #define H6_R_CLK_APB1 2 #define H6_R_CLK_APB2 3 #define H6_R_CLK_APB2_I2C 8 +#define H6_R_CLK_APB2_RSB 13 struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = { [H6_R_CLK_APB1] = { 0xffff, 0xff }, - [H6_R_CLK_APB2_I2C] = { 0x019c, 1, H6_R_CLK_APB2 }, + [H6_R_CLK_APB2_I2C] = { 0x019c, 0, H6_R_CLK_APB2 }, + [H6_R_CLK_APB2_RSB] = { 0x01bc, 0, H6_R_CLK_APB2 }, }; /* R40 */ @@ -833,6 +844,10 @@ struct sxiccmu_ccu_bit sun8i_h3_r_resets #define H6_RST_BUS_UART1 22 #define H6_RST_BUS_UART2 23 #define H6_RST_BUS_UART3 24 +#define H6_RST_BUS_EMAC 33 +#define H6_RST_USB_PHY0 44 +#define H6_RST_USB_PHY1 45 +#define H6_RST_USB_PHY3 46 #define H6_RST_BUS_OHCI0 48 #define H6_RST_BUS_OHCI3 49 #define H6_RST_BUS_EHCI0 50 @@ -846,6 +861,10 @@ struct sxiccmu_ccu_bit sun50i_h6_resets[ [H6_RST_BUS_UART1] = { 0x090c, 17 }, [H6_RST_BUS_UART2] = { 0x090c, 18 }, [H6_RST_BUS_UART3] = { 0x090c, 19 }, + [H6_RST_BUS_EMAC] = { 0x097c, 16 }, + [H6_RST_USB_PHY0] = { 0x0a70, 30 }, + [H6_RST_USB_PHY1] = { 0x0a74, 30 }, + [H6_RST_USB_PHY3] = { 0x0a7c, 30 }, [H6_RST_BUS_OHCI0] = { 0x0a8c, 16 }, [H6_RST_BUS_OHCI3] = { 0x0a8c, 19 }, [H6_RST_BUS_EHCI0] = { 0x0a8c, 20 }, @@ -853,9 +872,11 @@ struct sxiccmu_ccu_bit sun50i_h6_resets[ }; #define H6_R_RST_APB2_I2C 4 +#define H6_R_RST_APB2_RSB 7 struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = { [H6_R_RST_APB2_I2C] = { 0x019c, 16 }, + [H6_R_RST_APB2_RSB] = { 0x01bc, 16 }, }; /* R40 */ Index: dev/ic/com.c =================================================================== RCS file: /cvs/src/sys/dev/ic/com.c,v retrieving revision 1.174 diff -u -p -u -p -r1.174 com.c --- dev/ic/com.c 6 May 2021 20:35:21 -0000 1.174 +++ dev/ic/com.c 26 Nov 2021 20:44:39 -0000 @@ -1300,7 +1300,7 @@ void com_attach_subr(struct com_softc *sc) { int probe = 0; - u_int8_t lcr; + u_int8_t lcr, fifo; sc->sc_ier = 0; /* disable interrupts */ @@ -1480,6 +1480,25 @@ com_attach_subr(struct com_softc *sc) SET(sc->sc_hwflags, COM_HW_FIFO); sc->sc_fifolen = 256; break; + case COM_UART_DW_APB: + printf(": DesignWare APB UART, "); + SET(sc->sc_hwflags, COM_HW_FIFO); + sc->sc_fifolen = CPR_FIFO_MODE(com_read_reg(sc, com_cpr)) * 16; + if (sc->sc_fifolen) { + printf("%d byte fifo\n", sc->sc_fifolen); + } else { + printf("no fifo\n"); + /* + * Allwinner H6's DW-APB configuration does not have + * CPR register and detect as no fifo. + * But this UART has 256 bytes FIFO and disabling FIFO + * makes problem; LSR_RXRDY is still set after + * reading com_data when FIFO is disabled (errata?). + * For workaround, treat as 1 byte FIFO. + */ + sc->sc_fifolen = 1; + } + break; default: panic("comattach: bad fifo type"); } @@ -1496,10 +1515,13 @@ com_attach_subr(struct com_softc *sc) } /* clear and disable fifo */ - com_write_reg(sc, com_fifo, FIFO_RCV_RST | FIFO_XMT_RST); + /* DW-APB UART cannot turn off FIFO here (ddb will not work) */ + fifo = (sc->sc_uarttype == COM_UART_DW_APB) ? + (FIFO_ENABLE | FIFO_TRIGGER_1) : 0; + com_write_reg(sc, com_fifo, fifo | FIFO_RCV_RST | FIFO_XMT_RST); if (ISSET(com_read_reg(sc, com_lsr), LSR_RXRDY)) (void)com_read_reg(sc, com_data); - com_write_reg(sc, com_fifo, 0); + com_write_reg(sc, com_fifo, fifo); sc->sc_mcr = 0; com_write_reg(sc, com_mcr, sc->sc_mcr); Index: dev/ic/comreg.h =================================================================== RCS file: /cvs/src/sys/dev/ic/comreg.h,v retrieving revision 1.20 diff -u -p -u -p -r1.20 comreg.h --- dev/ic/comreg.h 14 Aug 2020 18:14:11 -0000 1.20 +++ dev/ic/comreg.h 26 Nov 2021 20:44:39 -0000 @@ -180,6 +180,9 @@ #define ISR_TXPL 0x08 /* negative transmit data polarity */ #define ISR_RXPL 0x10 /* negative receive data polarity */ +/* component parameter register (Synopsys DesignWare APB UART) */ +#define CPR_FIFO_MODE(x) (((x) >> 16) & 0xff) + #define COM_NPORTS 8 /* Exar XR17V35X */ Index: dev/ic/comvar.h =================================================================== RCS file: /cvs/src/sys/dev/ic/comvar.h,v retrieving revision 1.58 diff -u -p -u -p -r1.58 comvar.h --- dev/ic/comvar.h 14 Aug 2020 18:14:11 -0000 1.58 +++ dev/ic/comvar.h 26 Nov 2021 20:44:39 -0000 @@ -104,6 +104,7 @@ struct com_softc { #define COM_UART_XR16850 0x10 /* 128 byte fifo */ #define COM_UART_OX16C950 0x11 /* 128 byte fifo */ #define COM_UART_XR17V35X 0x12 /* 256 byte fifo */ +#define COM_UART_DW_APB 0x13 /* configurable */ u_char sc_hwflags; #define COM_HW_NOIEN 0x01 Index: dev/ic/ns16550reg.h =================================================================== RCS file: /cvs/src/sys/dev/ic/ns16550reg.h,v retrieving revision 1.5 diff -u -p -u -p -r1.5 ns16550reg.h --- dev/ic/ns16550reg.h 2 Jun 2003 23:28:02 -0000 1.5 +++ dev/ic/ns16550reg.h 26 Nov 2021 20:44:39 -0000 @@ -50,3 +50,9 @@ #define com_lsr 5 /* line status register (R/W) */ #define com_msr 6 /* modem status register (R/W) */ #define com_scratch 7 /* scratch register (R/W) */ + +/* + * Synopsys DesignWare APB UART additional registers + */ +#define com_usr 31 /* UART status register (R) */ +#define com_cpr 61 /* component parameter register (R) */
