> Date: Wed, 04 Sep 2019 19:30:34 +0900
> From: SASANO Takayoshi <u...@mx5.nisiq.net>
>
> hello,
>
> Here is the log that your patch applied kernel.
> It looks sxipio0 and sxipio1 is enabled.
Here is a start for H6 support in sxiccmu(4). Can you try this and
send me new console output?
Thanks,
Mark
Index: dev/fdt/sxiccmu.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
retrieving revision 1.23
diff -u -p -r1.23 sxiccmu.c
--- dev/fdt/sxiccmu.c 2 Sep 2019 13:08:49 -0000 1.23
+++ dev/fdt/sxiccmu.c 5 Sep 2019 14:55:35 -0000
@@ -144,7 +144,9 @@ sxiccmu_match(struct device *parent, voi
OF_is_compatible(node, "allwinner,sun9i-a80-mmc-config-clk") ||
OF_is_compatible(node, "allwinner,sun50i-a64-ccu") ||
OF_is_compatible(node, "allwinner,sun50i-a64-r-ccu") ||
- OF_is_compatible(node, "allwinner,sun50i-h5-ccu"));
+ OF_is_compatible(node, "allwinner,sun50i-h5-ccu") ||
+ OF_is_compatible(node, "allwinner,sun50i-h6-ccu") ||
+ OF_is_compatible(node, "allwinner,sun50i-h6-r-ccu"));
}
void
@@ -255,6 +257,22 @@ sxiccmu_attach(struct device *parent, st
sc->sc_nresets = nitems(sun50i_a64_resets);
sc->sc_get_frequency = sxiccmu_a64_get_frequency;
sc->sc_set_frequency = sxiccmu_a64_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun50i-h6-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun50i_h6_gates;
+ sc->sc_ngates = nitems(sun50i_h6_gates);
+ sc->sc_resets = sun50i_h6_resets;
+ sc->sc_nresets = nitems(sun50i_h6_resets);
+ sc->sc_get_frequency = sxiccmu_nop_get_frequency;
+ sc->sc_set_frequency = sxiccmu_nop_set_frequency;
+ } else if (OF_is_compatible(node, "allwinner,sun50i-h6-r-ccu")) {
+ KASSERT(faa->fa_nreg > 0);
+ sc->sc_gates = sun50i_h6_r_gates;
+ sc->sc_ngates = nitems(sun50i_h6_r_gates);
+ sc->sc_resets = sun50i_h6_r_resets;
+ sc->sc_nresets = nitems(sun50i_h6_r_resets);
+ sc->sc_get_frequency = sxiccmu_nop_get_frequency;
+ sc->sc_set_frequency = sxiccmu_nop_set_frequency;
} else {
for (node = OF_child(node); node; node = OF_peer(node))
sxiccmu_attach_clock(sc, node, faa->fa_nreg);
Index: dev/fdt/sxiccmu_clocks.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
retrieving revision 1.26
diff -u -p -r1.26 sxiccmu_clocks.h
--- dev/fdt/sxiccmu_clocks.h 2 Sep 2019 15:24:39 -0000 1.26
+++ dev/fdt/sxiccmu_clocks.h 5 Sep 2019 14:55:35 -0000
@@ -387,6 +387,50 @@ struct sxiccmu_ccu_bit sun8i_h3_r_gates[
[H3_R_CLK_APB0_I2C] = { 0x0028, 6, H3_R_CLK_APB0 },
};
+/* H6 */
+
+#define H6_CLK_MMC0 64
+#define H6_CLK_MMC1 65
+#define H6_CLK_MMC2 66
+#define H6_CLK_BUS_MMC0 67
+#define H6_CLK_BUS_MMC1 68
+#define H6_CLK_BUS_MMC2 69
+#define H6_CLK_BUS_UART0 70
+#define H6_CLK_BUS_UART1 71
+#define H6_CLK_BUS_UART2 72
+#define H6_CLK_BUS_UART3 73
+#define H6_CLK_USB_OHCI0 104
+#define H6_CLK_USB_OHCI3 107
+#define H6_CLK_BUS_OHCI0 111
+#define H6_CLK_BUS_OHCI3 112
+#define H6_CLK_BUS_EHCI0 113
+#define H6_CLK_BUS_EHCI3 115
+
+struct sxiccmu_ccu_bit sun50i_h6_gates[] = {
+ [H6_CLK_MMC0] = { 0x0830, 31 },
+ [H6_CLK_MMC1] = { 0x0834, 31 },
+ [H6_CLK_MMC2] = { 0x0838, 31 },
+ [H6_CLK_BUS_MMC0] = { 0x084c, 0 },
+ [H6_CLK_BUS_MMC1] = { 0x084c, 1 },
+ [H6_CLK_BUS_MMC2] = { 0x084c, 2 },
+ [H6_CLK_BUS_UART0] = { 0x090c, 0 },
+ [H6_CLK_BUS_UART1] = { 0x090c, 1 },
+ [H6_CLK_BUS_UART2] = { 0x090c, 2 },
+ [H6_CLK_BUS_UART3] = { 0x090c, 3 },
+ [H6_CLK_USB_OHCI0] = { 0x0a70, 31 },
+ [H6_CLK_USB_OHCI3] = { 0x0a7c, 31 },
+ [H6_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
+ [H6_CLK_BUS_OHCI3] = { 0x0a8c, 3 },
+ [H6_CLK_BUS_EHCI0] = { 0x0a8c, 4 },
+ [H6_CLK_BUS_EHCI3] = { 0x0a8c, 7 },
+};
+
+#define H6_R_CLK_APB2_I2C 8
+
+struct sxiccmu_ccu_bit sun50i_h6_r_gates[] = {
+ [H6_R_CLK_APB2_I2C] = { 0x019c, 1 },
+};
+
/* R40 */
#define R40_CLK_PLL_PERIPH0 11
@@ -722,6 +766,40 @@ struct sxiccmu_ccu_bit sun8i_h3_resets[]
struct sxiccmu_ccu_bit sun8i_h3_r_resets[] = {
[H3_R_RST_APB0_RSB] = { 0x00b0, 3 },
[H3_R_RST_APB0_I2C] = { 0x00b0, 6 },
+};
+
+/* H6 */
+
+#define H6_RST_BUS_MMC0 18
+#define H6_RST_BUS_MMC1 19
+#define H6_RST_BUS_MMC2 20
+#define H6_RST_BUS_UART0 21
+#define H6_RST_BUS_UART1 22
+#define H6_RST_BUS_UART2 23
+#define H6_RST_BUS_UART3 24
+#define H6_RST_BUS_OHCI0 48
+#define H6_RST_BUS_OHCI3 49
+#define H6_RST_BUS_EHCI0 50
+#define H6_RST_BUS_EHCI3 52
+
+struct sxiccmu_ccu_bit sun50i_h6_resets[] = {
+ [H6_RST_BUS_MMC0] = { 0x084c, 16 },
+ [H6_RST_BUS_MMC1] = { 0x084c, 17 },
+ [H6_RST_BUS_MMC2] = { 0x084c, 18 },
+ [H6_RST_BUS_UART0] = { 0x090c, 16 },
+ [H6_RST_BUS_UART1] = { 0x090c, 17 },
+ [H6_RST_BUS_UART2] = { 0x090c, 18 },
+ [H6_RST_BUS_UART3] = { 0x090c, 19 },
+ [H6_RST_BUS_OHCI0] = { 0x0a8c, 16 },
+ [H6_RST_BUS_OHCI3] = { 0x0a8c, 19 },
+ [H6_RST_BUS_EHCI0] = { 0x0a8c, 20 },
+ [H6_RST_BUS_EHCI3] = { 0x0a8c, 23 },
+};
+
+#define H6_R_RST_APB2_I2C 4
+
+struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = {
+ [H6_R_RST_APB2_I2C] = { 0x019c, 16 },
};
/* R40 */
