Hi, I am still struggling Allwinner H6's UART.
To compare behavior of UART, I tried NetBSD-current on Orange Pi One Plus.
NetBSD recognizes Allwinner H6's UART without FIFO.
[ 1.0000030] com0 at simplebus1: DesignWare APB UART, no fifo
[ 1.0000030] com0: console
[ 1.0000030] com0: interrupting on GIC irq 32
But it works with FIFO. Checked via ddb.
UART0 registers are mapped from 0xffffffff_f3400000.
login: Stopped in pid 0.26 (system) at netbsd:cpu_Debugger+0x4: ret
db{2}> x/x fffffffff3400000
fffffffff3400000: d
db{2}>
fffffffff3400004: 5
db{2}>
fffffffff3400008: c1
Register at 0xffffffff_f3400008 is IIR(read)/FCR(write).
IIR's bit [7:6] tells FIFO is enabled.
Writing some values to registers, disabling FIFO causes same problem.
db{2}> w fffffffff3400000 55
fffffffff3400000 = 55
Udb{2}> w fffffffff3400008 1
fffffffff3400008 = 1
db{2}> w fffffffff3400008 0
db{2}> aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
kaboom!
After disabling FIFO, UART's DR (Data Ready) bit at LSR register is
cleared and set when data received.
But read data from RBR register at that time, DR is still set
(normally cleared).
I think this should be called errata, but almost all users turns on FIFO
(from ARM's trusted firmware, through U-Boot, and finally running OS)
no one finds this problem.
To avoid problem of FIFO, I heard that com_fdt.c sets UART type as 16550
(not 16550A). But simply changing 16550 -> 16550A does not resolve this
problem. It looks Synopsys DesignWare UART (DW_UART) specific code is
needed, but I have no more idea.
Regards,
--
SASANO Takayoshi (JG1UAA) <u...@mx5.nisiq.net>
