> From: "Stephen Graf" <s_g...@telus.net> > Date: Mon, 28 Aug 2017 10:30:51 -0700 > > I tied your suggested change with the following results. > Not yet what I am thinking is correct.
> sxirtc0 at simplebus0 > A0 mux 7<invalid>- skipping > A1 mux 7<invalid>- skipping > A2 mux 7<invalid>- skipping > A3 mux 7<invalid>- skipping > A4 mux 2<uart0>- skipping > A5 mux 2<uart0>- skipping > A6 mux 7<invalid>- skipping > A7 mux 7<invalid>- skipping > A8 mux 7<invalid>- skipping > A9 mux 7<invalid>- skipping > A10 mux 7<invalid>- skipping > A11 mux 7<invalid>- skipping > A12 mux 7<invalid>- skipping > A13 mux 7<invalid>- skipping > A14 mux 7<invalid>- skipping > A15 mux 7<invalid>- skipping > A16 mux 7<invalid>- skipping > A17 mux 7<invalid>- skipping > A18 mux 7<invalid>- skipping > A19 mux 7<invalid>- skipping > A20 mux 7<invalid>- skipping > A21 mux 7<invalid>- skipping > C0 mux 7<invalid>- skipping > C1 mux 7<invalid>- skipping > C2 mux 7<invalid>- skipping > C3 mux 7<invalid>- skipping > C4 mux 7<invalid>- skipping > C5 mux 7<invalid>- skipping > C6 mux 7<invalid>- skipping > C7 mux 7<invalid>- skipping > C8 mux 7<invalid>- skipping > C9 mux 7<invalid>- skipping > C10 mux 7<invalid>- skipping > C11 mux 7<invalid>- skipping > C12 mux 7<invalid>- skipping > C13 mux 7<invalid>- skipping > C14 mux 7<invalid>- skipping > C15 mux 7<invalid>- skipping > C16 mux 7<invalid>- skipping > D0 mux 7<invalid>- skipping > D1 mux 7<invalid>- skipping > D2 mux 7<invalid>- skipping > D3 mux 7<invalid>- skipping > D4 mux 7<invalid>- skipping > D5 mux 7<invalid>- skipping > D6 mux 7<invalid>- skipping > D7 mux 7<invalid>- skipping > D8 mux 7<invalid>- skipping > D9 mux 7<invalid>- skipping > D10 mux 7<invalid>- skipping > D11 mux 7<invalid>- skipping > D12 mux 7<invalid>- skipping > D13 mux 7<invalid>- skipping > D14 mux 7<invalid>- skipping > D15 mux 7<invalid>- skipping > D16 mux 7<invalid>- skipping > D17 mux 7<invalid>- skipping > E0 mux 7<invalid>- skipping > E1 mux 7<invalid>- skipping > E2 mux 7<invalid>- skipping > E3 mux 7<invalid>- skipping > E4 mux 7<invalid>- skipping > E5 mux 7<invalid>- skipping > E6 mux 7<invalid>- skipping > E7 mux 7<invalid>- skipping > E8 mux 7<invalid>- skipping > E9 mux 7<invalid>- skipping > E10 mux 7<invalid>- skipping > E11 mux 7<invalid>- skipping > E12 mux 7<invalid>- skipping > E13 mux 7<invalid>- skipping > E14 mux 7<invalid>- skipping > E15 mux 7<invalid>- skipping > F0 mux 2<mmc0>- skipping > F1 mux 2<mmc0>- skipping > F2 mux 2<mmc0>- skipping > F3 mux 2<mmc0>- skipping > F4 mux 2<mmc0>- skipping > F5 mux 2<mmc0>- skipping > F6 mux 0<gpio_in>- adding > G0 mux 7<invalid>- skipping > G1 mux 7<invalid>- skipping > G2 mux 7<invalid>- skipping > G3 mux 7<invalid>- skipping > G4 mux 7<invalid>- skipping > G5 mux 7<invalid>- skipping > G6 mux 7<invalid>- skipping > G7 mux 7<invalid>- skipping > G8 mux 7<invalid>- skipping > G9 mux 7<invalid>- skipping > G10 mux 7<invalid>- skipping > G11 mux 7<invalid>- skipping > G12 mux 7<invalid>- skipping > G13 mux 7<invalid>- skipping > gpio0 at sxipio0: 32 pins > gpio1 at sxipio0: 32 pins > gpio2 at sxipio0: 32 pins > gpio3 at sxipio0: 32 pins > gpio4 at sxipio0: 32 pins > gpio5 at sxipio0: 32 pins > gpio6 at sxipio0: 32 pins > A0 mux 7<invalid>- skipping > A1 mux 7<invalid>- skipping > A2 mux 7<invalid>- skipping > A3 mux 7<invalid>- skipping > A4 mux 7<invalid>- skipping > A5 mux 7<invalid>- skipping > A6 mux 7<invalid>- skipping > A7 mux 7<invalid>- skipping > A8 mux 7<invalid>- skipping > A9 mux 7<invalid>- skipping > A10 mux 7<invalid>- skipping > A11 mux 7<invalid>- skipping > gpio7 at sxipio1: 32 pins Actually this starts to make sense. If you look at page 316 and further of the H3 data sheet: http://linux-sunxi.org/images/4/4b/Allwinner_H3_Datasheet_V1.2.pdf you'll see that the pins most pins come up in state 7 "IO disable". I think we can allow configurtion of pins thet are left in this state without too much risk. I don't have much time to look into this right now myself. But please remind me in the 2nd half of september if nothing happens before then.
