On Sat, 22 Nov 2008, Bob Netherton wrote:

>
>> In other words, for random access across a working set larger (by 
>> say X%) than the SSD-backed L2 ARC, the cache is useless.  This 
>> should asymptotically approach truth as X grows and experience 
>> shows that X=200% is where it's about 99% true.
>>
> Ummm, before we throw around phrases like useless, how about a 
> little testing ?  I like a good academic argument just like the next 
> guy, but before I dismiss something completely out of hand I'd like 
> to see some data.

This argument can be proven by basic statistics without need to resort 
to actual testing.

A similar issue applies to non-volatile write caches.

Luckily, most data access is not completely random in nature.

Bob
======================================
Bob Friesenhahn
[EMAIL PROTECTED], http://www.simplesystems.org/users/bfriesen/
GraphicsMagick Maintainer,    http://www.GraphicsMagick.org/

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