These features are marked experimental (for only parts of the code actually having got tested yet, while other parts require respective hardware) and opt-in for guests.
Signed-off-by: Jan Beulich <jbeul...@suse.com> --- v3: New. --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -6,6 +6,9 @@ The format is based on [Keep a Changelog ## [unstable UNRELEASED](https://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=staging) - TBD +### Added / support upgraded + - x86 AMX and XFD (Experimental) + ## [4.15.0 UNRELEASED](https://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=RELEASE-4.15.0) - TBD ### Added / support upgraded --- a/SUPPORT.md +++ b/SUPPORT.md @@ -61,6 +61,10 @@ For the Cortex A57 r0p0 - r1p1, see Erra Status: Tech Preview +### x86 AMX and XFD + + Status: Experimental + ### IOMMU Status, AMD IOMMU: Supported --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -191,7 +191,7 @@ XEN_CPUFEATURE(XSAVEOPT, 4*32+ 0) / XEN_CPUFEATURE(XSAVEC, 4*32+ 1) /*A XSAVEC/XRSTORC instructions */ XEN_CPUFEATURE(XGETBV1, 4*32+ 2) /*A XGETBV with %ecx=1 */ XEN_CPUFEATURE(XSAVES, 4*32+ 3) /*S XSAVES/XRSTORS instructions */ -XEN_CPUFEATURE(XFD, 4*32+ 4) /* XFD / XFD_ERR MSRs */ +XEN_CPUFEATURE(XFD, 4*32+ 4) /*a XFD / XFD_ERR MSRs */ /* Intel-defined CPU features, CPUID level 0x00000007:0.ebx, word 5 */ XEN_CPUFEATURE(FSGSBASE, 5*32+ 0) /*A {RD,WR}{FS,GS}BASE instructions */ @@ -269,9 +269,9 @@ XEN_CPUFEATURE(MD_CLEAR, 9*32+10) / XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ XEN_CPUFEATURE(SERIALIZE, 9*32+14) /*a SERIALIZE insn */ XEN_CPUFEATURE(CET_IBT, 9*32+20) /* CET - Indirect Branch Tracking */ -XEN_CPUFEATURE(AMX_BF16, 9*32+22) /* AMX BFloat16 instructions */ -XEN_CPUFEATURE(AMX_TILE, 9*32+24) /* AMX tile architecture */ -XEN_CPUFEATURE(AMX_INT8, 9*32+25) /* AMX 8-bit integer instructions */ +XEN_CPUFEATURE(AMX_BF16, 9*32+22) /*a AMX BFloat16 instructions */ +XEN_CPUFEATURE(AMX_TILE, 9*32+24) /*a AMX tile architecture */ +XEN_CPUFEATURE(AMX_INT8, 9*32+25) /*a AMX 8-bit integer instructions */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */
