On 14/01/2020 10:02, Jan Beulich wrote:
> FIFO event channels allow ports up to 2^17, so we need to use a wider
> field in struct pirq. Move "masked" such that it may share the 8-byte
> slot with struct arch_pirq on 64-bit arches, rather than leaving a
> 7-byte hole in all cases.
>
> Take the opportunity and also add a comment regarding "arch" placement
> within the structure.
>
> Signed-off-by: Jan Beulich <jbeul...@suse.com>
Oops. In fairness, it was entirely reasonable of the FIFO work to
presume that all code already used evtchn_port_t for evtchn ports.
Acked-by: Andrew Cooper <andrew.coop...@citrix.com>
>
> --- a/xen/include/xen/irq.h
> +++ b/xen/include/xen/irq.h
> @@ -127,9 +127,10 @@ struct vcpu;
>
> struct pirq {
> int pirq;
> - u16 evtchn;
> - bool_t masked;
> + evtchn_port_t evtchn;
> struct rcu_head rcu_head;
> + bool masked;
> + /* Architectures may require this field to be last. */
> struct arch_pirq arch;
> };
>
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