Hi Jan,
On 14/01/2020 10:02, Jan Beulich wrote:
FIFO event channels allow ports up to 2^17, so we need to use a wider
field in struct pirq. Move "masked" such that it may share the 8-byte
slot with struct arch_pirq on 64-bit arches, rather than leaving a
7-byte hole in all cases.
Take the opportunity and also add a comment regarding "arch" placement
within the structure.
Signed-off-by: Jan Beulich <jbeul...@suse.com>
--- a/xen/include/xen/irq.h
+++ b/xen/include/xen/irq.h
@@ -127,9 +127,10 @@ struct vcpu;
struct pirq {
int pirq;
- u16 evtchn;
- bool_t masked;
+ evtchn_port_t evtchn;
struct rcu_head rcu_head;
+ bool masked;
+ /* Architectures may require this field to be last. */
I orginally planned to add a comment in struct pirq, but I am not in
favor to continue to encourage quirkiness in the code. I sent a series
(see [1]) that drop this requirements from x86 and therefore remove the
need of this comment.
struct arch_pirq arch;
};
Cheers,
[1]
https://lists.xenproject.org/archives/html/xen-devel/2020-01/msg00924.html
--
Julien Grall
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
